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https://github.com/m-labs/artiq.git
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artiq_flash: add preinit-command option
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parent
6089d44fd0
commit
4a57b52241
@ -5,6 +5,7 @@ import os
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import subprocess
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import tempfile
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import shutil
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from functools import partial
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from artiq import __artiq_dir__ as artiq_dir
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from artiq.frontend.bit2bin import bit2bin
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@ -38,8 +39,10 @@ Prerequisites:
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help="target board, default: %(default)s")
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parser.add_argument("-m", "--adapter", default=None,
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help="target adapter, default: board-dependent")
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parser.add_argument("--target-file", default=None,
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help="use alternative OpenOCD target file")
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parser.add_argument("--preinit-command", default=[], action="append",
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help="add a pre-initialization OpenOCD command. "
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"Useful for selecting a development board "
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"when several are connected.")
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parser.add_argument("-f", "--storage", help="write file to storage area")
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parser.add_argument("-d", "--dir", help="look for files in this directory")
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parser.add_argument("action", metavar="ACTION", nargs="*",
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@ -67,10 +70,15 @@ def proxy_path():
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class Programmer:
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def __init__(self, target_file):
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def __init__(self, target_file, preinit_commands):
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self.target_file = target_file
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self.preinit_commands = preinit_commands
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self.prog = []
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def init(self):
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self.prog.extend(self.preinit_commands)
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self.prog.append("init")
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def load(self, bitfile):
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raise NotImplementedError
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@ -96,9 +104,10 @@ class Programmer:
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class ProgrammerJtagSpi7(Programmer):
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def __init__(self, target_file):
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Programmer.__init__(self, target_file)
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self.prog.append("init")
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def __init__(self, target, preinit_commands):
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Programmer.__init__(self, os.path.join("board", target + ".cfg"),
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preinit_commands)
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self.init()
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def load(self, bitfile):
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self.prog.append("pld load 0 " + bitfile)
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@ -117,10 +126,9 @@ class ProgrammerJtagSpi7(Programmer):
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class ProgrammerSayma(Programmer):
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def __init__(self, target_file):
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# TODO: use target_file
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def __init__(self, preinit_commands):
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# TODO: support Sayma RTM
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Programmer.__init__(self, None)
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Programmer.__init__(self, None, preinit_commands)
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self.proxy_loaded = False
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self.prog += [
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"interface ftdi",
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@ -149,9 +157,8 @@ class ProgrammerSayma(Programmer):
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"target create amc_xcu.proxy testee -chain-position amc_xcu.tap",
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"flash bank amc_xcu.spi0 jtagspi 0 0 0 0 amc_xcu.proxy $XILINX_USER1 $AMC_DR_LEN",
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"flash bank amc_xcu.spi1 jtagspi 0 0 0 0 amc_xcu.proxy $XILINX_USER2 $AMC_DR_LEN",
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"init"
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]
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self.init()
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def load(self, bitfile):
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self.prog.append("pld load 0 " + bitfile)
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@ -180,7 +187,7 @@ def main():
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config = {
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"kc705": {
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"programmer_factory": ProgrammerJtagSpi7,
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"programmer_factory": partial(ProgrammerJtagSpi7, "kc705"),
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"proxy_bitfile": "bscan_spi_xc7k325t.bit",
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"adapters": ["nist_clock", "nist_qc2"],
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"gateware": (0, 0x000000),
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@ -216,11 +223,7 @@ def main():
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raise SystemExit("Binaries directory '{}' does not exist"
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.format(bin_dir))
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if opts.target_file is None:
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target_file = os.path.join("board", opts.target + ".cfg")
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else:
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target_file = opts.target_file
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programmer = config["programmer_factory"](target_file)
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programmer = config["programmer_factory"](opts.preinit_command)
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conv = False
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for action in opts.action:
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