diff --git a/artiq/gateware/serwb/phy.py b/artiq/gateware/serwb/phy.py index 49beb9240..eb1050c66 100644 --- a/artiq/gateware/serwb/phy.py +++ b/artiq/gateware/serwb/phy.py @@ -13,7 +13,7 @@ from artiq.gateware.serwb.s7phy import S7Serdes # 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle pattern. # 3) Slave sends K28.5 commas to allow Master to calibrate, Master sends K28.5 commas. # 4) Master stops sending K28.5 commas. -# 5) Slave stops sending K25.5 commas. +# 5) Slave stops sending K28.5 commas. # 6) Link is ready. class _SerdesMasterInit(Module): @@ -120,13 +120,8 @@ class _SerdesMasterInit(Module): NextValue(delay_max_found, 0), NextState("WAIT_STABLE") ).Else( - NextState("RESET_SAMPLING_WINDOW") - ) - ) - fsm.act("RESET_SAMPLING_WINDOW", - NextValue(delay, 0), - serdes.rx_delay_rst.eq(1), - NextState("WAIT_SAMPLING_WINDOW"), + NextState("CONFIGURE_SAMPLING_WINDOW") + ), serdes.tx_comma.eq(1) ) fsm.act("CONFIGURE_SAMPLING_WINDOW", @@ -246,13 +241,9 @@ class _SerdesSlaveInit(Module, AutoCSR): NextValue(delay_max_found, 0), NextState("WAIT_STABLE") ).Else( - NextState("RESET_SAMPLING_WINDOW") - ) - ) - fsm.act("RESET_SAMPLING_WINDOW", - NextValue(delay, 0), - serdes.rx_delay_rst.eq(1), - NextState("WAIT_SAMPLING_WINDOW") + NextState("CONFIGURE_SAMPLING_WINDOW") + ), + serdes.tx_idle.eq(1) ) fsm.act("CONFIGURE_SAMPLING_WINDOW", If(delay == (delay_min + (delay_max - delay_min)[1:]), @@ -368,9 +359,15 @@ class SERWBPLL(Module): p_CLKOUT2_DIVIDE=8//vco_div, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_serwb_serdes_5x_clk ), - Instance("BUFG", i_I=pll_serwb_serdes_clk, o_O=self.serwb_serdes_clk), - Instance("BUFG", i_I=pll_serwb_serdes_20x_clk, o_O=self.serwb_serdes_20x_clk), - Instance("BUFG", i_I=pll_serwb_serdes_5x_clk, o_O=self.serwb_serdes_5x_clk) + Instance("BUFG", + i_I=pll_serwb_serdes_clk, + o_O=self.serwb_serdes_clk), + Instance("BUFG", + i_I=pll_serwb_serdes_20x_clk, + o_O=self.serwb_serdes_20x_clk), + Instance("BUFG", + i_I=pll_serwb_serdes_5x_clk, + o_O=self.serwb_serdes_5x_clk) ] self.specials += MultiReg(pll_locked, self.lock)