From 47e3106c4eef3df1a3ffef5656d42d8f1157dd93 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 7 Jun 2016 11:08:05 -0400
Subject: [PATCH] gateware/nist_clock: increase DDS bus drive strength. Closes
 #468

---
 artiq/gateware/nist_clock.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/nist_clock.py b/artiq/gateware/nist_clock.py
index b6db05efe..1f63111d1 100644
--- a/artiq/gateware/nist_clock.py
+++ b/artiq/gateware/nist_clock.py
@@ -36,7 +36,7 @@ fmc_adapter_io = [
         Subsignal("wr_n", Pins("LPC:LA24_P")),
         Subsignal("rd_n", Pins("LPC:LA25_N")),
         Subsignal("rst", Pins("LPC:LA25_P")),
-        IOStandard("LVTTL")),
+        IOStandard("LVTTL"), Misc("DRIVE=24")),
 
     ("i2c_fmc", 0,
         Subsignal("scl", Pins("LPC:IIC_SCL")),