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artiq
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moninj: fix underflows by order of operation 

fix channel toggle
This commit is contained in:
mwojcik 2022-07-07 12:30:09 +08:00 committed by Sébastien Bourdeauducq
parent c9fb7b410f
commit 46f2842d38
1 changed files with 6 additions and 6 deletions
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12
artiq/dashboard/moninj.py
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@ -560,7 +560,7 @@ class _DeviceManager:
if len(cfg) > 0:
self.{cpld}.cfg_reg = cfg[0]
else:
delay(10*ms)
delay(15*ms)
self.{cpld}.init()
self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
cfg = self.core_cache.get("_{cpld}_cfg")
@ -584,8 +584,8 @@ class _DeviceManager:
@kernel
def run(self):
self.core.reset()
delay(5*ms)
{cpld_init}
delay(5*ms)
self.{dds_channel}.init()
self.{dds_channel}.set({freq})
{cfg_sw}
@ -598,7 +598,7 @@ class _DeviceManager:
"SetDDS",
"Set DDS {} {}MHz".format(dds_channel, freq/1e6)))
def dds_channel_toggle(self, dds_model, sw=True):
def dds_channel_toggle(self, dds_channel, dds_model, sw=True):
# urukul only
toggle_exp = textwrap.dedent("""
from artiq.experiment import *
@ -612,16 +612,16 @@ class _DeviceManager:
@kernel
def run(self):
self.core.break_realtime()
delay(5*ms)
self.core.reset()
cfg = self.core_cache.get("_{cpld}_cfg")
if len(cfg) > 0:
self.{cpld}.cfg_reg = cfg[0]
else:
delay(10*ms)
delay(15*ms)
self.{cpld}.init()
self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
cfg = self.core_cache.get("_{cpld}_cfg")
delay(5*ms)
self.{ch}.init()
self.{ch}.cfg_sw({sw})
cfg[0] = self.{cpld}.cfg_reg