M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
Code Issues Projects Releases Wiki Activity

phaser: update stpl

Browse Source
This commit is contained in:
Robert Jördens 2016-10-12 14:22:21 +02:00
parent 5f737bef76
commit 466d1e8304
1 changed files with 38 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
artiq/examples/phaser/repository/test_ad9154_stpl.py
View File

@ -1,4 +1,4 @@
import time from jesd204b.transport import seed_to_data
from artiq.coredevice.ad9154_reg import * from artiq.coredevice.ad9154_reg import *
from artiq.experiment import * from artiq.experiment import *
@ -10,36 +10,41 @@ class Test(EnvExperiment):
self.setattr_device("ad9154") self.setattr_device("ad9154")
def run(self): def run(self):
self.stpl() self.ad9154.jesd_stpl(0)
def stpl(self):
# short transport layer test # short transport layer test
for i, data in enumerate([0x0123, 0x4567, 0x89ab, 0xcdef]): for i in range(4):
# select dac data = seed_to_data(i << 8, True)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0, fail = self.stpl(i, data)
AD9154_SHORT_TPL_TEST_EN_SET(0) | print("channel", i, "FAIL" if fail else "PASS")
AD9154_SHORT_TPL_TEST_RESET_SET(0) | self.ad9154.jesd_stpl(0)
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0)) @kernel
# set expected value def stpl(self, i, data):
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff) # select dac
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8) self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
# enable stpl AD9154_SHORT_TPL_TEST_EN_SET(0) |
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0, AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_TEST_EN_SET(1) | AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) | AD9154_SHORT_TPL_SP_SEL_SET(0))
AD9154_SHORT_TPL_DAC_SEL_SET(i) | # set expected value
AD9154_SHORT_TPL_SP_SEL_SET(0)) self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
# reset stpl self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0, # enable stpl
AD9154_SHORT_TPL_TEST_EN_SET(1) | self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_RESET_SET(1) | AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) | AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_SP_SEL_SET(0)) AD9154_SHORT_TPL_DAC_SEL_SET(i) |
# release reset stpl AD9154_SHORT_TPL_SP_SEL_SET(0))
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0, # reset stpl
AD9154_SHORT_TPL_TEST_EN_SET(1) | self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_RESET_SET(0) | AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) | AD9154_SHORT_TPL_TEST_RESET_SET(1) |
AD9154_SHORT_TPL_SP_SEL_SET(0)) AD9154_SHORT_TPL_DAC_SEL_SET(i) |
print("c{:d}: {:d}".format(i, self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3))) AD9154_SHORT_TPL_SP_SEL_SET(0))
# release reset stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
return self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)