mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 19:28:26 +08:00
Merge branch 'master' into nac3
This commit is contained in:
commit
45edb9e0f7
@ -12,6 +12,7 @@ Highlights:
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- Kasli-SoC, a new EEM carrier based on a Zynq SoC, enabling much faster kernel execution.
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- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotinos
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- Almazny mezzanine board for Mirny
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* TTL device output can be now configured to work as a clock generator.
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* Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx).
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* Gateware FPU is supported on KC705 and Kasli 2.0.
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* Faster compilation for large arrays/lists.
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@ -110,9 +110,10 @@ class CommMgmt:
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return ty
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def _read_expect(self, ty):
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if self._read_header() != ty:
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header = self._read_header()
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if header != ty:
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raise IOError("Incorrect reply from device: {} (expected {})".
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format(self._read_type, ty))
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format(header, ty))
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def _read_int32(self):
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(value, ) = struct.unpack(self.endian + "l", self._read(4))
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@ -159,7 +160,12 @@ class CommMgmt:
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def config_read(self, key):
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self._write_header(Request.ConfigRead)
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self._write_string(key)
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self._read_expect(Reply.ConfigData)
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ty = self._read_header()
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if ty == Reply.Error:
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raise IOError("Device failed to read config. The key may not exist.")
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elif ty != Reply.ConfigData:
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raise IOError("Incorrect reply from device: {} (expected {})".
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format(ty, Reply.ConfigData))
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return self._read_string()
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def config_write(self, key, value):
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@ -170,11 +170,11 @@
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},
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"bank_direction_low": {
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"type": "string",
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"enum": ["input", "output"]
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"enum": ["input", "output", "clkgen"]
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},
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"bank_direction_high": {
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"type": "string",
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"enum": ["input", "output"]
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"enum": ["input", "output", "clkgen"]
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}
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},
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"required": ["ports", "bank_direction_low", "bank_direction_high"]
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@ -14,6 +14,12 @@ from artiq.gui.scientific_spinbox import ScientificSpinBox
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logger = logging.getLogger(__name__)
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async def rename(key, newkey, value, dataset_ctl):
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if key != newkey:
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await dataset_ctl.delete(key)
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await dataset_ctl.set(newkey, value)
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class Editor(QtWidgets.QDialog):
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def __init__(self, parent, dataset_ctl, key, value):
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QtWidgets.QDialog.__init__(self, parent=parent)
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@ -26,7 +32,11 @@ class Editor(QtWidgets.QDialog):
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self.setLayout(grid)
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grid.addWidget(QtWidgets.QLabel("Name:"), 0, 0)
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grid.addWidget(QtWidgets.QLabel(key), 0, 1)
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self.name_widget = QtWidgets.QLineEdit()
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self.name_widget.setText(key)
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grid.addWidget(self.name_widget, 0, 1)
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grid.addWidget(QtWidgets.QLabel("Value:"), 1, 0)
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grid.addWidget(self.get_edit_widget(value), 1, 1)
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@ -39,8 +49,9 @@ class Editor(QtWidgets.QDialog):
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buttons.rejected.connect(self.reject)
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def accept(self):
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newkey = self.name_widget.text()
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value = self.initial_type(self.get_edit_widget_value())
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asyncio.ensure_future(self.dataset_ctl.set(self.key, value))
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asyncio.ensure_future(rename(self.key, newkey, value, self.dataset_ctl))
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QtWidgets.QDialog.accept(self)
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def get_edit_widget(self, initial_value):
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@ -203,6 +203,7 @@ _WidgetDesc = namedtuple("_WidgetDesc", "uid comment cls arguments")
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def setup_from_ddb(ddb):
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mi_addr = None
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mi_port = None
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dds_sysclk = None
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description = set()
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@ -235,14 +236,16 @@ def setup_from_ddb(ddb):
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description.add(widget)
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elif v["type"] == "controller" and k == "core_moninj":
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mi_addr = v["host"]
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mi_port = v.get("port_proxy", 1383)
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except KeyError:
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pass
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return mi_addr, dds_sysclk, description
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return mi_addr, mi_port, dds_sysclk, description
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class _DeviceManager:
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def __init__(self):
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self.mi_addr = None
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self.mi_port = None
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self.reconnect_mi = asyncio.Event()
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self.mi_connection = None
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self.mi_connector_task = asyncio.ensure_future(self.mi_connector())
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@ -264,10 +267,11 @@ class _DeviceManager:
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return ddb
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def notify(self, mod):
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mi_addr, dds_sysclk, description = setup_from_ddb(self.ddb)
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mi_addr, mi_port, dds_sysclk, description = setup_from_ddb(self.ddb)
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if mi_addr != self.mi_addr:
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if (mi_addr, mi_port) != (self.mi_addr, self.mi_port):
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self.mi_addr = mi_addr
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self.mi_port = mi_port
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self.reconnect_mi.set()
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self.dds_sysclk = dds_sysclk
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@ -397,7 +401,7 @@ class _DeviceManager:
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new_mi_connection = CommMonInj(self.monitor_cb, self.injection_status_cb,
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self.disconnect_cb)
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try:
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await new_mi_connection.connect(self.mi_addr, 1383)
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await new_mi_connection.connect(self.mi_addr, self.mi_port)
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except asyncio.CancelledError:
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logger.info("cancelled connection to moninj")
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break
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@ -9,6 +9,7 @@ pub enum Error {
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MissingSeparator { offset: usize },
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Utf8Error(str::Utf8Error),
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NoFlash,
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KeyNotFound
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}
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impl fmt::Display for Error {
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@ -28,6 +29,8 @@ impl fmt::Display for Error {
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write!(f, "{}", err),
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&Error::NoFlash =>
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write!(f, "flash memory is not present"),
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&Error::KeyNotFound =>
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write!(f, "key not found")
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}
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}
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}
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@ -156,14 +159,16 @@ mod imp {
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f(Lock::take().and_then(|lock| {
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let mut iter = Iter::new(lock.data());
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let mut value = &[][..];
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let mut found = false;
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while let Some(result) = iter.next() {
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let (record_key, record_value) = result?;
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if key.as_bytes() == record_key {
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found = true;
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// last write wins
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value = record_value
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}
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}
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Ok(value)
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if found { Ok(value) } else { Err(Error::KeyNotFound) }
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}))
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}
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@ -529,7 +529,7 @@ fn flash_kernel_worker(io: &Io, aux_mutex: &Mutex,
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config::read(config_key, |result| {
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match result {
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Ok(kernel) if kernel.len() > 0 => unsafe {
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Ok(kernel) => unsafe {
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// kernel CPU cannot access the SPI flash address space directly,
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// so make a copy.
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kern_load(io, &mut session, Vec::from(kernel).as_ref())
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@ -7,7 +7,10 @@ import socket
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import ssl
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import io
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import zipfile
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import json
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from prettytable import PrettyTable
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from getpass import getpass
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from tqdm import tqdm
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def get_artiq_cert():
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@ -54,20 +57,42 @@ class Client:
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self.fsocket.write((" ".join(command) + "\n").encode())
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self.fsocket.flush()
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def read_line(self):
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return self.fsocket.readline().decode("ascii")
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def read_reply(self):
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return self.fsocket.readline().decode("ascii").split()
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def read_json(self):
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return json.loads(self.fsocket.readline().decode("ascii"))
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def login(self, username, password):
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self.send_command("LOGIN", username, password)
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return self.read_reply() == ["HELLO"]
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def build(self, rev, variant):
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self.send_command("BUILD", rev, variant)
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def build(self, rev, variant, log):
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if not variant:
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variants = self.get_variants()
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if len(variants) != 1:
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raise ValueError("User can build more than 1 variant - need to specify")
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variant = variants[0][0]
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print("Building variant: {}".format(variant))
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if log:
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self.send_command("BUILD", rev, variant, "LOG_ENABLE")
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else:
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self.send_command("BUILD", rev, variant)
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reply = self.read_reply()[0]
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if reply != "BUILDING":
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return reply, None
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print("Build in progress. This may take 10-15 minutes.")
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reply, status = self.read_reply()
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if log:
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line = self.read_line()
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while line != "" and line.startswith("LOG"):
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print(line[4:], end="")
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line = self.read_line()
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reply, status = line.split()
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else:
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reply, status = self.read_reply()
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if reply != "DONE":
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raise ValueError("Unexpected server reply: expected 'DONE', got '{}'".format(reply))
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if status != "done":
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@ -76,7 +101,15 @@ class Client:
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reply, length = self.read_reply()
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if reply != "PRODUCT":
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raise ValueError("Unexpected server reply: expected 'PRODUCT', got '{}'".format(reply))
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contents = self.fsocket.read(int(length))
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length = int(length)
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contents = bytearray()
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with tqdm(total=length, unit="iB", unit_scale=True, unit_divisor=1024) as progress_bar:
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total = 0
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while total != length:
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chunk_len = min(4096, length-total)
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contents += self.fsocket.read(chunk_len)
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total += chunk_len
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progress_bar.update(chunk_len)
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print("Download completed.")
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return "OK", contents
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@ -84,6 +117,13 @@ class Client:
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self.send_command("PASSWD", password)
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return self.read_reply() == ["OK"]
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def get_variants(self):
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self.send_command("GET_VARIANTS")
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reply = self.read_reply()[0]
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if reply != "OK":
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raise ValueError("Unexpected server reply: expected 'OK', got '{}'".format(reply))
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return self.read_json()
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def main():
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parser = argparse.ArgumentParser()
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@ -95,9 +135,11 @@ def main():
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action.required = True
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act_build = action.add_parser("build", help="build and download firmware")
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act_build.add_argument("--rev", default=None, help="revision to build (default: currently installed ARTIQ revision)")
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act_build.add_argument("variant", help="variant to build")
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act_build.add_argument("--log", action="store_true", help="Display the build log")
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act_build.add_argument("directory", help="output directory")
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act_build.add_argument("variant", nargs="?", default=None, help="variant to build (can be omitted if user is authorised to build only one)")
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act_passwd = action.add_parser("passwd", help="change password")
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act_get_variants = action.add_parser("get_variants", help="get available variants and expiry dates")
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args = parser.parse_args()
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cert = args.cert
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@ -146,14 +188,22 @@ def main():
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if rev is None:
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print("Unable to determine currently installed ARTIQ revision. Specify manually using --rev.")
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sys.exit(1)
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result, contents = client.build(rev, args.variant)
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result, contents = client.build(rev, args.variant, args.log)
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if result != "OK":
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if result == "UNAUTHORIZED":
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print("You are not authorized to build this variant. Your firmware subscription may have expired. Contact helpdesk\x40m-labs.hk.")
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elif result == "TOOMANY":
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print("Too many builds in a queue. Please wait for others to finish.")
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else:
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print("Build failed: {}".format(result))
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sys.exit(1)
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zip_unarchive(contents, args.directory)
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elif args.action == "get_variants":
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data = client.get_variants()
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table = PrettyTable()
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table.field_names = ["Variant", "Expiry date"]
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table.add_rows(data)
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print(table)
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else:
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raise ValueError
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finally:
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@ -94,7 +94,8 @@ class PeripheralManager:
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def process_dio(self, rtio_offset, peripheral, num_channels=8):
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class_names = {
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"input": "TTLInOut",
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"output": "TTLOut"
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"output": "TTLOut",
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"clkgen": "TTLClockGen"
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}
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classes = [
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class_names[peripheral["bank_direction_low"]],
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@ -231,10 +231,8 @@ class Urukul(_EEM):
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = target.platform.request("urukul{}_dds_reset_sync_in".format(eem))
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pad = Signal(reset=0)
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target.specials += DifferentialOutput(pad, pads.p, pads.n)
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if sync_gen_cls is not None: # AD9910 variant and SYNC_IN from EEM
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phy = sync_gen_cls(pad, ftw_width=4)
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phy = sync_gen_cls(pad=pads.p, pad_n=pads.n, ftw_width=4)
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -5,7 +5,8 @@ from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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def peripheral_dio(module, peripheral, **kwargs):
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ttl_classes = {
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"input": ttl_serdes_7series.InOut_8X,
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"output": ttl_serdes_7series.Output_8X
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"output": ttl_serdes_7series.Output_8X,
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"clkgen": ttl_simple.ClockGen
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}
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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@ -145,11 +145,16 @@ class InOut(Module):
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class ClockGen(Module):
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def __init__(self, pad, ftw_width=24):
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def __init__(self, pad, pad_n=None, ftw_width=24, dci=False):
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self.rtlink = rtlink.Interface(rtlink.OInterface(ftw_width))
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# # #
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pad_o = Signal()
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if pad_n is None:
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self.comb += pad.eq(pad_o)
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else:
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self.specials += DifferentialOutput(pad_o, pad, pad_n)
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ftw = Signal(ftw_width)
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acc = Signal(ftw_width)
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self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data))
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@ -165,5 +170,5 @@ class ClockGen(Module):
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acc.eq(0)
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)
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),
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pad.eq(acc[-1])
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pad_o.eq(acc[-1])
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]
|
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|
Loading…
Reference in New Issue
Block a user