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ad9858: make wb data 8 bit wide 

matches actual dds bus data width and saves bram
This commit is contained in:
Robert Jördens 2015-06-20 23:33:55 -06:00
parent c8fba45db5
commit 45ec5dbe84
1 changed files with 1 additions and 1 deletions
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artiq/gateware/ad9858.py
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@ -38,7 +38,7 @@ class AD9858(Module):
read_wait_cycles=10, hiz_wait_cycles=3, read_wait_cycles=10, hiz_wait_cycles=3,
bus=None): bus=None):
if bus is None: if bus is None:
bus = wishbone.Interface() bus = wishbone.Interface(data_width=8)
self.bus = bus self.bus = bus
# # # # # #