diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index c6970f71d..e38441707 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -25,6 +25,8 @@ Highlights: * Core device: ``panic_reset 1`` now correctly resets the kernel CPU as well if communication CPU panic occurs. * NumberValue accepts a ``type`` parameter specifying the output as ``int`` or ``float`` +* A parameter `--identifier-str` has been added to many targets to aid + with reproducible builds. Breaking changes: diff --git a/artiq/build_soc.py b/artiq/build_soc.py index c5487d8d7..2770c2ff3 100644 --- a/artiq/build_soc.py +++ b/artiq/build_soc.py @@ -44,10 +44,12 @@ class ReprogrammableIdentifier(Module, AutoCSR): p_INIT=sum(1 << j if c & (1 << i) else 0 for j, c in enumerate(contents))) -def add_identifier(soc, *args, **kwargs): +def add_identifier(soc, *args, identifier_str=None, **kwargs): if hasattr(soc, "identifier"): raise ValueError - identifier_str = get_identifier_string(soc, *args, **kwargs) + if identifier_str is None: + # not overridden with --identifier-str + identifier_str = get_identifier_string(soc, *args, **kwargs) soc.submodules.identifier = ReprogrammableIdentifier(identifier_str) soc.config["IDENTIFIER_STR"] = identifier_str diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 73162c65b..902f00047 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -99,7 +99,7 @@ class StandaloneBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, **kwargs): + def __init__(self, identifier_str=None, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -109,7 +109,7 @@ class StandaloneBase(MiniSoC, AMPSoC): ethmac_ntxslots=4, **kwargs) AMPSoC.__init__(self) - add_identifier(self) + add_identifier(self, identifier_str=identifier_str) if self.platform.hw_rev == "v2.0": self.submodules.error_led = gpio.GPIOOut(Cat( @@ -280,7 +280,7 @@ class MasterBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, rtio_clk_freq=125e6, enable_sata=False, **kwargs): + def __init__(self, rtio_clk_freq=125e6, enable_sata=False, identifier_str=None, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -290,7 +290,7 @@ class MasterBase(MiniSoC, AMPSoC): ethmac_ntxslots=4, **kwargs) AMPSoC.__init__(self) - add_identifier(self) + add_identifier(self, identifier_str=identifier_str) platform = self.platform @@ -453,13 +453,13 @@ class SatelliteBase(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, **kwargs): + def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, identifier_str=None, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", l2_size=128*1024, **kwargs) - add_identifier(self) + add_identifier(self, identifier_str=identifier_str) platform = self.platform @@ -674,11 +674,14 @@ def main(): help="variant: {} (default: %(default)s)".format( "/".join(sorted(VARIANTS.keys())))) parser.add_argument("--with-wrpll", default=False, action="store_true") + parser.add_argument("--identifier-str", default=None, + help="Override ROM identifier") args = parser.parse_args() argdict = dict() if args.with_wrpll: argdict["with_wrpll"] = True + argdict["identifier_str"] = args.identifier_str variant = args.variant.lower() try: diff --git a/artiq/gateware/targets/kasli_generic.py b/artiq/gateware/targets/kasli_generic.py index bae599ed9..7109fc150 100755 --- a/artiq/gateware/targets/kasli_generic.py +++ b/artiq/gateware/targets/kasli_generic.py @@ -252,6 +252,8 @@ def main(): parser.set_defaults(output_dir="artiq_kasli") parser.add_argument("description", metavar="DESCRIPTION", help="JSON system description file") + parser.add_argument("--identifier-str", default=None, + help="Override ROM identifier") args = parser.parse_args() with open(args.description, "r") as f: @@ -269,7 +271,7 @@ def main(): else: raise ValueError("Invalid base") - soc = cls(description, **soc_kasli_argdict(args)) + soc = cls(description, identifier_str=args.identifier_str, **soc_kasli_argdict(args)) args.variant = description["variant"] build_artiq_soc(soc, builder_argdict(args)) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index b586edda4..aa9fe96b7 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -119,7 +119,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, **kwargs): + def __init__(self, identifier_str=None, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -129,7 +129,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): ethmac_ntxslots=4, **kwargs) AMPSoC.__init__(self) - add_identifier(self) + add_identifier(self, identifier_str=identifier_str) if isinstance(self.platform.toolchain, XilinxVivadoToolchain): self.platform.toolchain.bitstream_commands.extend([ @@ -416,6 +416,8 @@ def main(): help="variant: " "nist_clock/nist_qc2/sma_spi " "(default: %(default)s)") + parser.add_argument("--identifier-str", default=None, + help="Override ROM identifier") args = parser.parse_args() variant = args.variant.lower() @@ -424,7 +426,7 @@ def main(): except KeyError: raise SystemExit("Invalid variant (-V/--variant)") - soc = cls(**soc_kc705_argdict(args)) + soc = cls(identifier_str=args.identifier_str, **soc_kc705_argdict(args)) build_artiq_soc(soc, builder_argdict(args)) diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py index d1013653c..9c255f79d 100755 --- a/artiq/gateware/targets/metlino.py +++ b/artiq/gateware/targets/metlino.py @@ -38,7 +38,7 @@ class Master(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, **kwargs): + def __init__(self, identifier_str=None, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -49,7 +49,7 @@ class Master(MiniSoC, AMPSoC): csr_address_width=15, **kwargs) AMPSoC.__init__(self) - add_identifier(self) + add_identifier(self, identifier_str=identifier_str) platform = self.platform rtio_clk_freq = 150e6 @@ -164,9 +164,11 @@ def main(): builder_args(parser) soc_sdram_args(parser) parser.set_defaults(output_dir="artiq_metlino") + parser.add_argument("--identifier-str", default=None, + help="Override ROM identifier") args = parser.parse_args() args.variant = "master" - soc = Master(**soc_sdram_argdict(args)) + soc = Master(identifier_str=args.identifier_str, **soc_sdram_argdict(args)) build_artiq_soc(soc, builder_argdict(args)) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index c2cb435f1..90e486e2f 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -50,7 +50,7 @@ class SatelliteBase(MiniSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", with_sfp=False, *, with_wrpll, **kwargs): + def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -59,7 +59,7 @@ class SatelliteBase(MiniSoC): ethmac_nrxslots=4, ethmac_ntxslots=4, **kwargs) - add_identifier(self, suffix=identifier_suffix) + add_identifier(self, suffix=identifier_suffix, identifier_str=identifier_str) self.rtio_clk_freq = rtio_clk_freq platform = self.platform @@ -403,14 +403,24 @@ def main(): help="Change type of signal generator. This is used exclusively for " "development and debugging.") parser.add_argument("--with-wrpll", default=False, action="store_true") + parser.add_argument("--identifier-str", default=None, + help="Override ROM identifier") args = parser.parse_args() variant = args.variant.lower() if variant == "satellite": - soc = Satellite(with_sfp=args.sfp, jdcg_type=args.jdcg_type, with_wrpll=args.with_wrpll, - **soc_sayma_amc_argdict(args)) + soc = Satellite( + with_sfp=args.sfp, + jdcg_type=args.jdcg_type, + with_wrpll=args.with_wrpll, + identifier_str=args.identifier_str, + **soc_sayma_amc_argdict(args)) elif variant == "simplesatellite": - soc = SimpleSatellite(with_sfp=args.sfp, with_wrpll=args.with_wrpll, **soc_sayma_amc_argdict(args)) + soc = SimpleSatellite( + with_sfp=args.sfp, + with_wrpll=args.with_wrpll, + identifier_str=args.identifier_str, + **soc_sayma_amc_argdict(args)) else: raise SystemExit("Invalid variant (-V/--variant)") diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index bdef1fa09..0a670e04e 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -75,11 +75,11 @@ class _SatelliteBase(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, rtio_clk_freq, *, with_wrpll, **kwargs): + def __init__(self, rtio_clk_freq, *, with_wrpll, identifier_str, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", **kwargs) - add_identifier(self) + add_identifier(self, identifier_str=identifier_str) self.rtio_clk_freq = rtio_clk_freq platform = self.platform @@ -299,11 +299,15 @@ def main(): parser.add_argument("--rtio-clk-freq", default=150, type=int, help="RTIO clock frequency in MHz") parser.add_argument("--with-wrpll", default=False, action="store_true") + parser.add_argument("--identifier-str", default=None, + help="Override ROM identifier") parser.set_defaults(output_dir=os.path.join("artiq_sayma", "rtm")) args = parser.parse_args() soc = Satellite( - rtio_clk_freq=1e6*args.rtio_clk_freq, with_wrpll=args.with_wrpll, + rtio_clk_freq=1e6*args.rtio_clk_freq, + with_wrpll=args.with_wrpll, + identifier_str=args.identifier_str, **soc_sayma_rtm_argdict(args)) builder = SatmanSoCBuilder(soc, **builder_argdict(args)) try: