mirror of https://github.com/m-labs/artiq.git
pipistrello: shrink fifos a bit more to relax pnr
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ecda94705e
commit
454b48df97
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@ -176,7 +176,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
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self.rtio_crg.rtiox4_stb)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
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ofifo_depth=4))
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# the last TTL is used for ClockGen
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@ -191,7 +191,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128))
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phy = ttl_simple.Output(platform.request("ext_led", 0))
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self.submodules += phy
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@ -202,19 +202,17 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
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spi_pins = self.platform.request("pmod_extended_spi", 0)
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi.SPIMaster(spi_pins)
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phy = spi.SPIMaster(self.platform.request("pmod_extended_spi", 0))
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self.submodules += phy
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=256, ififo_depth=256))
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phy, ofifo_depth=64, ififo_depth=64))
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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@ -225,7 +223,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ofifo_depth=256,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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