mirror of https://github.com/m-labs/artiq.git
wrpll/thls: rework instruction decoding
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2776c5b16b
commit
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@ -45,17 +45,19 @@ class SubIsn(Isn):
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class MulShiftIsn(Isn):
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class MulShiftIsn(Isn):
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opcode = 3
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opcode = 3
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# opcode = 4: MulShift with alternate shift
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class CopyIsn(Isn):
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class CopyIsn(Isn):
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opcode = 4
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opcode = 7
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class InputIsn(Isn):
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class InputIsn(Isn):
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opcode = 5
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opcode = 8
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class OutputIsn(Isn):
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class OutputIsn(Isn):
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opcode = 6
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opcode = 9
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class EndIsn(Isn):
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class EndIsn(Isn):
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opcode = 7
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opcode = 10
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class ASTCompiler:
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class ASTCompiler:
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@ -139,7 +141,7 @@ class Processor:
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self.multiplier_shifts = []
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self.multiplier_shifts = []
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self.program_rom_size = None
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self.program_rom_size = None
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self.data_ram_size = None
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self.data_ram_size = None
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self.opcode_bits = 3
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self.opcode_bits = 4
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self.reg_bits = None
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self.reg_bits = None
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def get_instruction_latency(self, isn):
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def get_instruction_latency(self, isn):
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@ -472,8 +474,7 @@ class ProcessorImpl(Module):
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units = [nop, adder, subtractor, multiplier, copier, inu, outu]
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units = [nop, adder, subtractor, multiplier, copier, inu, outu]
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self.submodules += units
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self.submodules += units
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for n, unit in enumerate(units):
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for unit in units:
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self.sync += unit.stb_i.eq(pc_en & (opcode == n))
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self.comb += [
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self.comb += [
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unit.i0.eq(data_read_port0.dat_r),
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unit.i0.eq(data_read_port0.dat_r),
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unit.i1.eq(data_read_port1.dat_r),
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unit.i1.eq(data_read_port1.dat_r),
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@ -483,6 +484,19 @@ class ProcessorImpl(Module):
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)
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)
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]
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]
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decode_table = [
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(NopIsn.opcode, nop),
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(AddIsn.opcode, adder),
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(SubIsn.opcode, subtractor),
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(MulShiftIsn.opcode, multiplier),
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(MulShiftIsn.opcode + 1, multiplier),
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(CopyIsn.opcode, copier),
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(InputIsn.opcode, inu),
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(OutputIsn.opcode, outu)
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]
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for allocated_opcode, unit in decode_table:
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self.sync += unit.stb_i.eq(pc_en & (opcode == allocated_opcode))
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fsm = FSM()
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fsm = FSM()
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self.submodules += fsm
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self.submodules += fsm
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fsm.act("IDLE",
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fsm.act("IDLE",
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