wrpll/thls: rework instruction decoding

This commit is contained in:
Sebastien Bourdeauducq 2019-08-15 15:55:13 +08:00
parent 2776c5b16b
commit 44969b03ad
1 changed files with 21 additions and 7 deletions

View File

@ -45,17 +45,19 @@ class SubIsn(Isn):
class MulShiftIsn(Isn): class MulShiftIsn(Isn):
opcode = 3 opcode = 3
# opcode = 4: MulShift with alternate shift
class CopyIsn(Isn): class CopyIsn(Isn):
opcode = 4 opcode = 7
class InputIsn(Isn): class InputIsn(Isn):
opcode = 5 opcode = 8
class OutputIsn(Isn): class OutputIsn(Isn):
opcode = 6 opcode = 9
class EndIsn(Isn): class EndIsn(Isn):
opcode = 7 opcode = 10
class ASTCompiler: class ASTCompiler:
@ -139,7 +141,7 @@ class Processor:
self.multiplier_shifts = [] self.multiplier_shifts = []
self.program_rom_size = None self.program_rom_size = None
self.data_ram_size = None self.data_ram_size = None
self.opcode_bits = 3 self.opcode_bits = 4
self.reg_bits = None self.reg_bits = None
def get_instruction_latency(self, isn): def get_instruction_latency(self, isn):
@ -472,8 +474,7 @@ class ProcessorImpl(Module):
units = [nop, adder, subtractor, multiplier, copier, inu, outu] units = [nop, adder, subtractor, multiplier, copier, inu, outu]
self.submodules += units self.submodules += units
for n, unit in enumerate(units): for unit in units:
self.sync += unit.stb_i.eq(pc_en & (opcode == n))
self.comb += [ self.comb += [
unit.i0.eq(data_read_port0.dat_r), unit.i0.eq(data_read_port0.dat_r),
unit.i1.eq(data_read_port1.dat_r), unit.i1.eq(data_read_port1.dat_r),
@ -483,6 +484,19 @@ class ProcessorImpl(Module):
) )
] ]
decode_table = [
(NopIsn.opcode, nop),
(AddIsn.opcode, adder),
(SubIsn.opcode, subtractor),
(MulShiftIsn.opcode, multiplier),
(MulShiftIsn.opcode + 1, multiplier),
(CopyIsn.opcode, copier),
(InputIsn.opcode, inu),
(OutputIsn.opcode, outu)
]
for allocated_opcode, unit in decode_table:
self.sync += unit.stb_i.eq(pc_en & (opcode == allocated_opcode))
fsm = FSM() fsm = FSM()
self.submodules += fsm self.submodules += fsm
fsm.act("IDLE", fsm.act("IDLE",