From 444b901dbec5c9ef50b712043344666a76a30159 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 16 Jan 2018 07:28:00 +0000
Subject: [PATCH] sayma: add RTM configuration port.

---
 artiq/gateware/targets/sayma_amc_standalone.py | 6 ++++++
 conda/artiq-dev/meta.yaml                      | 4 ++--
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py
index 7c8429175..b84ff4d26 100755
--- a/artiq/gateware/targets/sayma_amc_standalone.py
+++ b/artiq/gateware/targets/sayma_amc_standalone.py
@@ -7,6 +7,7 @@ from collections import namedtuple
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from misoc.cores.slave_fpga import SlaveFPGA
 from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
 from misoc.integration.builder import builder_args, builder_argdict
 from misoc.interconnect import stream
@@ -147,6 +148,11 @@ class Standalone(MiniSoC, AMPSoC):
             serial_rtm.tx.eq(serial_1.rx)
         ]
 
+        # RTM bitstream upload
+        rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
+        self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
+        self.csr_devices.append("rtm_fpga_cfg")
+
         # AMC/RTM serwb
         serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=2)
         self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
diff --git a/conda/artiq-dev/meta.yaml b/conda/artiq-dev/meta.yaml
index 76031427b..bdb83b29e 100644
--- a/conda/artiq-dev/meta.yaml
+++ b/conda/artiq-dev/meta.yaml
@@ -14,8 +14,8 @@ requirements:
   run:
     - python >=3.5.3,<3.6
     - setuptools 33.1.1
-    - migen 0.6.dev py35_64+gitc6ffa44
-    - misoc 0.8 py35_14+git97f1b8a6
+    - migen 0.6 py35_2+git61a055f
+    - misoc 0.8 py35_15+gitc5082e52
     - jesd204b 0.4
     - microscope
     - binutils-or1k-linux >=2.27