soc,runtime: define RTIO FUD channel number in targets

soc/runtime/rtio.c

@@ -91,8 +91,6 @@ int rtio_pileup_count(int channel)
     return r;
 }
 
-#define RTIO_FUD_CHANNEL 8
-
 void rtio_fud_sync(void)
 {
     while(rtio_get_counter() < previous_fud_end_time);

soc/targets/artiq_kc705.py

@@ -52,6 +52,7 @@ class _Peripherals(BaseSoC):
         rtio_ins = [platform.request("pmt") for i in range(2)]
         rtio_outs = [platform.request("ttl", i) for i in range(16)]
         rtio_outs.append(platform.request("user_led", 2))
+        self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
         rtio_outs.append(fud)
 
         self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)

soc/targets/artiq_pipistrello.py

@@ -69,9 +69,10 @@ class _Peripherals(BaseSoC):
         rtio_ins = [platform.request("pmt", i) for i in range(2)]
         rtio_ins += [platform.request("xtrig", 0)]
         rtio_outs = [platform.request("ttl", i) for i in range(16)]
-        rtio_outs += [fud]
         rtio_outs += [platform.request("ext_led", 0)]
         rtio_outs += [platform.request("user_led", i) for i in range(2, 5)]
+        self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
+        rtio_outs.append(fud)
 
         self.submodules.rtiocrg = _RTIOCRG(platform)
         self.submodules.rtiophy = rtio.phy.SimplePHY(

soc/targets/artiq_ppro.py

@@ -78,7 +78,9 @@ class UP(BaseSoC):
             platform.request("ttl_h_tx_en").eq(1)
         ]
         rtio_ins = [platform.request("pmt") for i in range(2)]
-        rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud]
+        rtio_outs = [platform.request("ttl", i) for i in range(5)]
+        self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
+        rtio_outs.append(fud)
 
         self.submodules.rtiocrg = _RTIOMiniCRG(platform)
         self.submodules.rtiophy = rtio.phy.SimplePHY(