From 43ecb3fea6b1580a7563613181c86df1a8ad614a Mon Sep 17 00:00:00 2001
From: Harry Ho <hh@m-labs.hk>
Date: Tue, 15 Dec 2020 18:06:02 +0800
Subject: [PATCH] sayma: add comments about CPLL line rate on KU GTH

---
 artiq/gateware/targets/sayma_amc.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index 59fa820f7..4edfc72c7 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -192,6 +192,8 @@ class SatelliteBase(MiniSoC):
 # JESD204 DAC Channel Group
 class JDCGSAWG(Module, AutoCSR):
     def __init__(self, platform, sys_crg, jesd_crg, dac):
+        # Kintex Ultrascale GTH, speed grade -1C:
+        # CPLL linerate (D=1): 4.0 - 8.5 Gb/s
         self.submodules.jesd = jesd204_tools.UltrascaleTX(
             platform, sys_crg, jesd_crg, dac)