From 43d120359d5e63ded08ad7de99893f754b55e2e1 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 12 Aug 2021 11:54:36 +0800 Subject: [PATCH] compiler: switch to upstream llvmlite and RISC-V target --- artiq/compiler/targets.py | 21 +++++++++---------- artiq/compiler/testbench/jit.py | 2 +- artiq/compiler/testbench/llvmgen.py | 2 +- artiq/compiler/testbench/perf.py | 4 ++-- artiq/compiler/testbench/perf_embedding.py | 4 ++-- artiq/compiler/testbench/shlib.py | 4 ++-- .../compiler/transforms/llvm_ir_generator.py | 2 +- artiq/coredevice/core.py | 8 +++---- artiq/frontend/artiq_ddb_template.py | 2 +- artiq/frontend/artiq_run.py | 2 +- doc/manual/conf.py | 2 +- setup.py | 2 +- 12 files changed, 27 insertions(+), 28 deletions(-) diff --git a/artiq/compiler/targets.py b/artiq/compiler/targets.py index 9ebc7907d..745dede81 100644 --- a/artiq/compiler/targets.py +++ b/artiq/compiler/targets.py @@ -1,6 +1,6 @@ import os, sys, tempfile, subprocess, io from artiq.compiler import types, ir -from llvmlite_artiq import ir as ll, binding as llvm +from llvmlite import ir as ll, binding as llvm llvm.initialize() llvm.initialize_all_targets() @@ -67,7 +67,7 @@ class Target: generated by the ARTIQ compiler will be deployed. :var triple: (string) - LLVM target triple, e.g. ``"or1k"`` + LLVM target triple, e.g. ``"riscv32"`` :var data_layout: (string) LLVM target data layout, e.g. ``"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"`` :var features: (list of string) @@ -255,19 +255,18 @@ class NativeTarget(Target): assert host_data_layout[0] in "eE" self.little_endian = host_data_layout[0] == "e" -class OR1KTarget(Target): - triple = "or1k-linux" - data_layout = "E-m:e-p:32:32-i8:8:8-i16:16:16-i64:32:32-" \ - "f64:32:32-v64:32:32-v128:32:32-a0:0:32-n32" - features = ["mul", "div", "ffl1", "cmov", "addc"] +class RISCVTarget(Target): + triple = "riscv32-unknown-linux" + data_layout = "e-m:e-p:32:32-i64:64-n32-S128" + features = [] print_function = "core_log" little_endian = False now_pinning = True - tool_ld = "or1k-linux-ld" - tool_strip = "or1k-linux-strip" - tool_addr2line = "or1k-linux-addr2line" - tool_cxxfilt = "or1k-linux-c++filt" + tool_ld = "ld.lld" + tool_strip = "llvm-strip" + tool_addr2line = "llvm-addr2line" + tool_cxxfilt = "llvm-cxxfilt" class CortexA9Target(Target): triple = "armv7-unknown-linux-gnueabihf" diff --git a/artiq/compiler/testbench/jit.py b/artiq/compiler/testbench/jit.py index 309073404..67a43c008 100644 --- a/artiq/compiler/testbench/jit.py +++ b/artiq/compiler/testbench/jit.py @@ -1,6 +1,6 @@ import os, sys, fileinput, ctypes from pythonparser import diagnostic -from llvmlite_artiq import binding as llvm +from llvmlite import binding as llvm from ..module import Module, Source from ..targets import NativeTarget diff --git a/artiq/compiler/testbench/llvmgen.py b/artiq/compiler/testbench/llvmgen.py index ed318b897..6bcf031c9 100644 --- a/artiq/compiler/testbench/llvmgen.py +++ b/artiq/compiler/testbench/llvmgen.py @@ -1,6 +1,6 @@ import sys, fileinput from pythonparser import diagnostic -from llvmlite_artiq import ir as ll +from llvmlite import ir as ll from ..module import Module, Source from ..targets import NativeTarget diff --git a/artiq/compiler/testbench/perf.py b/artiq/compiler/testbench/perf.py index cee4e3c2a..363c88840 100644 --- a/artiq/compiler/testbench/perf.py +++ b/artiq/compiler/testbench/perf.py @@ -1,7 +1,7 @@ import sys, os from pythonparser import diagnostic from ..module import Module, Source -from ..targets import OR1KTarget +from ..targets import RISCVTarget from . import benchmark def main(): @@ -30,7 +30,7 @@ def main(): benchmark(lambda: Module(source), "ARTIQ transforms and validators") - benchmark(lambda: OR1KTarget().compile_and_link([module]), + benchmark(lambda: RISCVTarget().compile_and_link([module]), "LLVM optimization and linking") if __name__ == "__main__": diff --git a/artiq/compiler/testbench/perf_embedding.py b/artiq/compiler/testbench/perf_embedding.py index 41f09cb04..d626d5534 100644 --- a/artiq/compiler/testbench/perf_embedding.py +++ b/artiq/compiler/testbench/perf_embedding.py @@ -5,7 +5,7 @@ from ...master.databases import DeviceDB, DatasetDB from ...master.worker_db import DeviceManager, DatasetManager from ..module import Module from ..embedding import Stitcher -from ..targets import OR1KTarget +from ..targets import RISCVTarget from . import benchmark @@ -45,7 +45,7 @@ def main(): stitcher = embed() module = Module(stitcher) - target = OR1KTarget() + target = RISCVTarget() llvm_ir = target.compile(module) elf_obj = target.assemble(llvm_ir) elf_shlib = target.link([elf_obj]) diff --git a/artiq/compiler/testbench/shlib.py b/artiq/compiler/testbench/shlib.py index 47209a979..0aa6386d3 100644 --- a/artiq/compiler/testbench/shlib.py +++ b/artiq/compiler/testbench/shlib.py @@ -1,7 +1,7 @@ import sys, os from pythonparser import diagnostic from ..module import Module, Source -from ..targets import OR1KTarget +from ..targets import RISCVTarget def main(): if not len(sys.argv) > 1: @@ -20,7 +20,7 @@ def main(): for filename in sys.argv[1:]: modules.append(Module(Source.from_filename(filename, engine=engine))) - llobj = OR1KTarget().compile_and_link(modules) + llobj = RISCVTarget().compile_and_link(modules) basename, ext = os.path.splitext(sys.argv[-1]) with open(basename + ".so", "wb") as f: diff --git a/artiq/compiler/transforms/llvm_ir_generator.py b/artiq/compiler/transforms/llvm_ir_generator.py index 49fc339bd..10b83f3a7 100644 --- a/artiq/compiler/transforms/llvm_ir_generator.py +++ b/artiq/compiler/transforms/llvm_ir_generator.py @@ -6,7 +6,7 @@ into LLVM intermediate representation. import os, re, types as pytypes, numpy from collections import defaultdict from pythonparser import ast, diagnostic -from llvmlite_artiq import ir as ll, binding as llvm +from llvmlite import ir as ll, binding as llvm from ...language import core as language_core from .. import types, builtins, ir from ..embedding import SpecializedFunction diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py index d150df596..dc8207266 100644 --- a/artiq/coredevice/core.py +++ b/artiq/coredevice/core.py @@ -11,7 +11,7 @@ from artiq.language.units import * from artiq.compiler.module import Module from artiq.compiler.embedding import Stitcher -from artiq.compiler.targets import OR1KTarget, CortexA9Target +from artiq.compiler.targets import RISCVTarget, CortexA9Target from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy # Import for side effects (creating the exception classes). @@ -71,11 +71,11 @@ class Core: "core", "ref_period", "coarse_ref_period", "ref_multiplier", } - def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="or1k"): + def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="riscv"): self.ref_period = ref_period self.ref_multiplier = ref_multiplier - if target == "or1k": - self.target_cls = OR1KTarget + if target == "riscv": + self.target_cls = RISCVTarget elif target == "cortexa9": self.target_cls = CortexA9Target else: diff --git a/artiq/frontend/artiq_ddb_template.py b/artiq/frontend/artiq_ddb_template.py index c73680c8e..4dfba4f93 100755 --- a/artiq/frontend/artiq_ddb_template.py +++ b/artiq/frontend/artiq_ddb_template.py @@ -15,7 +15,7 @@ def process_header(output, description): raise NotImplementedError cpu_target = { - "kasli": "or1k", + "kasli": "riscv", "kasli_soc": "cortexa9" }[description["target"]] diff --git a/artiq/frontend/artiq_run.py b/artiq/frontend/artiq_run.py index 98e3c8221..21baf3f05 100755 --- a/artiq/frontend/artiq_run.py +++ b/artiq/frontend/artiq_run.py @@ -10,7 +10,7 @@ from collections import defaultdict import h5py -from llvmlite_artiq import binding as llvm +from llvmlite import binding as llvm from sipyco import common_args diff --git a/doc/manual/conf.py b/doc/manual/conf.py index 509816e80..bc092928f 100644 --- a/doc/manual/conf.py +++ b/doc/manual/conf.py @@ -37,7 +37,7 @@ mock_modules = ["artiq.gui.waitingspinnerwidget", "qasync", "pyqtgraph", "matplotlib", "numpy", "dateutil", "dateutil.parser", "prettytable", "PyQt5", "h5py", "serial", "scipy", "scipy.interpolate", - "llvmlite_artiq", "Levenshtein", "pythonparser", + "llvmlite", "Levenshtein", "pythonparser", "sipyco", "sipyco.pc_rpc", "sipyco.sync_struct", "sipyco.asyncio_tools", "sipyco.logging_tools", "sipyco.broadcast", "sipyco.packed_exceptions"] diff --git a/setup.py b/setup.py index 980e6b109..ed3ef26d2 100755 --- a/setup.py +++ b/setup.py @@ -15,7 +15,7 @@ requirements = [ "numpy", "scipy", "python-dateutil", "prettytable", "h5py", "qasync", "pyqtgraph", "pygit2", - "llvmlite_artiq", "pythonparser", "python-Levenshtein", + "llvmlite", "pythonparser", "python-Levenshtein", ] console_scripts = [