mirror of https://github.com/m-labs/artiq.git
sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite
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parent
476cfa0f53
commit
433273dd95
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@ -247,18 +247,21 @@ pub extern fn main() -> i32 {
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info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
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info!("gateware version {}", ident::read(&mut [0; 64]));
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#[cfg(has_slave_fpga_cfg)]
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board_artiq::slave_fpga::load().expect("cannot load RTM FPGA gateware");
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#[cfg(has_serwb_phy_amc)]
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serwb::wait_init();
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#[cfg(has_hmc830_7043)]
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/* must be the first SPI init because of HMC830 SPI mode selection */
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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i2c::init();
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si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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#[cfg(has_hmc830_7043)]
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/* must be the first SPI init because of HMC830 SPI mode selection */
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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loop {
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while !drtio_link_rx_up() {
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process_errors();
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@ -8,8 +8,6 @@ import warnings
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from microscope import *
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from misoc.cores import gpio
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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@ -152,26 +150,8 @@ class AD9154NoSAWG(Module, AutoCSR):
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]
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class Standalone(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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class RTMCommon:
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def __init__(self):
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platform = self.platform
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# forward RTM UART to second FTDI UART channel
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@ -204,8 +184,32 @@ class Standalone(MiniSoC, AMPSoC):
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self.submodules += serwb_core
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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class Standalone(MiniSoC, AMPSoC, RTMCommon):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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self.config["HMC830_REF"] = "100"
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platform = self.platform
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# RTIO
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rtio_channels = []
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for i in range(4):
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@ -270,12 +274,13 @@ class Standalone(MiniSoC, AMPSoC):
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self.csr_devices.append("rtio_analyzer")
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class Master(MiniSoC, AMPSoC):
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class Master(MiniSoC, AMPSoC, RTMCommon):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtio_aux": 0x50000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"drtio_aux": 0x14000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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@ -290,6 +295,8 @@ class Master(MiniSoC, AMPSoC):
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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self.config["HMC830_REF"] = "150"
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if with_sawg:
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warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
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@ -297,9 +304,6 @@ class Master(MiniSoC, AMPSoC):
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += Microscope(platform.request("serial", 1),
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self.clk_freq)
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# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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@ -390,9 +394,10 @@ class Master(MiniSoC, AMPSoC):
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self.register_kernel_cpu_csrdevice("cri_con")
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class Satellite(BaseSoC):
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class Satellite(BaseSoC, RTMCommon):
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mem_map = {
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"drtio_aux": 0x50000000,
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"serwb": 0x13000000,
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"drtio_aux": 0x14000000,
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}
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mem_map.update(BaseSoC.mem_map)
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@ -403,6 +408,8 @@ class Satellite(BaseSoC):
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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RTMCommon.__init__(self)
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self.config["HMC830_REF"] = "150"
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if with_sawg:
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warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
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@ -410,9 +417,6 @@ class Satellite(BaseSoC):
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += Microscope(platform.request("serial", 1),
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self.clk_freq)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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@ -508,8 +512,6 @@ def main():
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(with_sawg=not args.without_sawg, **soc_sdram_argdict(args))
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# DRTIO variants do not use the RTM yet.
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if variant not in {"master", "satellite"}:
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remote_csr_regions = remote_csr.get_remote_csr_regions(
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soc.mem_map["serwb"] | soc.shadow_base,
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args.rtm_csr_csv)
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