From 424a1f8f4e1af575fc171d55746d7a93e65b9a1e Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 16 Nov 2016 13:39:19 +0100 Subject: [PATCH] dsp: move test tools --- artiq/gateware/dsp/tools.py | 45 ---------------------------- artiq/test/gateware/test_accu.py | 2 +- artiq/test/gateware/test_sawg.py | 2 +- artiq/test/gateware/test_sawg_phy.py | 2 +- artiq/test/gateware/test_spline.py | 2 +- artiq/test/gateware/tools.py | 43 ++++++++++++++++++++++++++ 6 files changed, 47 insertions(+), 49 deletions(-) create mode 100644 artiq/test/gateware/tools.py diff --git a/artiq/gateware/dsp/tools.py b/artiq/gateware/dsp/tools.py index 1e220ecce..5ae78bd8c 100644 --- a/artiq/gateware/dsp/tools.py +++ b/artiq/gateware/dsp/tools.py @@ -4,32 +4,6 @@ from functools import reduce from migen import * -def set_dict(e, **k): - for k, v in k.items(): - if isinstance(v, dict): - yield from set_dict(getattr(e, k), **v) - else: - yield getattr(e, k).eq(v) - - -def xfer(dut, **kw): - ep = [] - for e, v in kw.items(): - e = getattr(dut, e) - yield from set_dict(e, **v) - ep.append(e) - for e in ep: - yield e.stb.eq(1) - while ep: - yield - for e in ep[:]: - if hasattr(e, "busy") and (yield e.busy): - raise ValueError(e, "busy") - if not hasattr(e, "ack") or (yield e.ack): - yield e.stb.eq(0) - ep.remove(e) - - class Delay(Module): def __init__(self, i, delay, o=None): if isinstance(i, (int, tuple)): @@ -73,22 +47,3 @@ class SatAddMixin: ) ] return s0 - - -def szip(*iters): - active = {it: None for it in iters} - while active: - for it in list(active): - while True: - try: - val = it.send(active[it]) - except StopIteration: - del active[it] - break - if val is None: - break - else: - active[it] = (yield val) - val = (yield None) - for it in active: - active[it] = val diff --git a/artiq/test/gateware/test_accu.py b/artiq/test/gateware/test_accu.py index 4bc7066fb..384fba9cc 100644 --- a/artiq/test/gateware/test_accu.py +++ b/artiq/test/gateware/test_accu.py @@ -4,7 +4,7 @@ from migen import * from migen.fhdl.verilog import convert from artiq.gateware.dsp.accu import Accu, PhasedAccu -from artiq.gateware.dsp.tools import xfer +from .tools import xfer def read(o, n): diff --git a/artiq/test/gateware/test_sawg.py b/artiq/test/gateware/test_sawg.py index 4ffd4ba78..00e5f8c3f 100644 --- a/artiq/test/gateware/test_sawg.py +++ b/artiq/test/gateware/test_sawg.py @@ -4,7 +4,7 @@ from migen import * from migen.fhdl.verilog import convert from artiq.gateware.dsp.sawg import DDSFast -from artiq.gateware.dsp.tools import xfer +from .tools import xfer def _test_gen_dds(dut, o): diff --git a/artiq/test/gateware/test_sawg_phy.py b/artiq/test/gateware/test_sawg_phy.py index 5b922968f..4f2617c7a 100644 --- a/artiq/test/gateware/test_sawg_phy.py +++ b/artiq/test/gateware/test_sawg_phy.py @@ -4,7 +4,7 @@ from migen import * from migen.fhdl.verilog import convert from artiq.gateware.rtio.phy.sawg import Channel -from artiq.gateware.dsp.tools import xfer, szip +from .tools import xfer, szip def rtio_xfer(dut, **kwargs): diff --git a/artiq/test/gateware/test_spline.py b/artiq/test/gateware/test_spline.py index 6fca4f555..fe2d82c28 100644 --- a/artiq/test/gateware/test_spline.py +++ b/artiq/test/gateware/test_spline.py @@ -4,7 +4,7 @@ from migen import * from migen.fhdl.verilog import convert from artiq.gateware.dsp.spline import Spline -from artiq.gateware.dsp.tools import xfer +from .tools import xfer def _test_gen_spline(dut, o): diff --git a/artiq/test/gateware/tools.py b/artiq/test/gateware/tools.py new file mode 100644 index 000000000..ca9451e78 --- /dev/null +++ b/artiq/test/gateware/tools.py @@ -0,0 +1,43 @@ +def set_dict(e, **k): + for k, v in k.items(): + if isinstance(v, dict): + yield from set_dict(getattr(e, k), **v) + else: + yield getattr(e, k).eq(v) + + +def xfer(dut, **kw): + ep = [] + for e, v in kw.items(): + e = getattr(dut, e) + yield from set_dict(e, **v) + ep.append(e) + for e in ep: + yield e.stb.eq(1) + while ep: + yield + for e in ep[:]: + if hasattr(e, "busy") and (yield e.busy): + raise ValueError(e, "busy") + if not hasattr(e, "ack") or (yield e.ack): + yield e.stb.eq(0) + ep.remove(e) + + +def szip(*iters): + active = {it: None for it in iters} + while active: + for it in list(active): + while True: + try: + val = it.send(active[it]) + except StopIteration: + del active[it] + break + if val is None: + break + else: + active[it] = (yield val) + val = (yield None) + for it in active: + active[it] = val