diff --git a/artiq/firmware/libboard_artiq/drtio_routing.rs b/artiq/firmware/libboard_artiq/drtio_routing.rs
index 4302cd880..c78b5cddd 100644
--- a/artiq/firmware/libboard_artiq/drtio_routing.rs
+++ b/artiq/firmware/libboard_artiq/drtio_routing.rs
@@ -75,8 +75,8 @@ pub fn program_interconnect(rt: &RoutingTable, rank: u8)
     for i in 0..DEST_COUNT {
         let hop = rt.0[i][rank as usize];
         unsafe {
-            csr::cri_con::routing_destination_write(i as _);
-            csr::cri_con::routing_hop_write(hop);
+            csr::routing_table::destination_write(i as _);
+            csr::routing_table::hop_write(hop);
         }
     }
 }
diff --git a/artiq/gateware/rtio/__init__.py b/artiq/gateware/rtio/__init__.py
index a144f593c..af4989f7c 100644
--- a/artiq/gateware/rtio/__init__.py
+++ b/artiq/gateware/rtio/__init__.py
@@ -1,5 +1,5 @@
 from artiq.gateware.rtio.tsc import TSC
-from artiq.gateware.rtio.cri import KernelInitiator, CRIInterconnectShared
+from artiq.gateware.rtio.cri import KernelInitiator, CRIInterconnectShared, RoutingTableAccess
 from artiq.gateware.rtio.channel import Channel, LogChannel
 from artiq.gateware.rtio.core import Core
 from artiq.gateware.rtio.analyzer import Analyzer
diff --git a/artiq/gateware/rtio/cri.py b/artiq/gateware/rtio/cri.py
index 0ed0d50e2..b60164ba2 100644
--- a/artiq/gateware/rtio/cri.py
+++ b/artiq/gateware/rtio/cri.py
@@ -119,28 +119,15 @@ class CRIDecoder(Module, AutoCSR):
         self.slaves = slaves
         self.master = master
 
-        slave_bits = bits_for(len(slaves)-1)
-        if enable_routing:
-            self.routing_destination = CSRStorage(8)
-            self.routing_hop = CSR(slave_bits)
-
         # # #
 
         # routing
+        slave_bits = bits_for(len(slaves)-1)
         selected = Signal(slave_bits)
 
         if enable_routing:
             self.specials.routing_table = Memory(slave_bits, 256)
 
-            rtp_csr = self.routing_table.get_port(write_capable=True)
-            self.specials += rtp_csr
-            self.comb += [
-                rtp_csr.adr.eq(self.routing_destination.storage),
-                rtp_csr.dat_w.eq(self.routing_hop.r),
-                rtp_csr.we.eq(self.routing_hop.re),
-                self.routing_hop.w.eq(rtp_csr.dat_r)
-            ]
-
             if mode == "async":
                 rtp_decoder = self.routing_table.get_port()
             elif mode == "sync":
@@ -220,3 +207,22 @@ class CRIInterconnectShared(Module):
 
     def get_csrs(self):
         return self.switch.get_csrs() + self.decoder.get_csrs()
+
+
+class RoutingTableAccess(Module, AutoCSR):
+    def __init__(self, interconnect):
+        if isinstance(interconnect, CRIInterconnectShared):
+            interconnect = interconnect.decoder
+
+        rtp_csr = interconnect.routing_table.get_port(write_capable=True)
+        self.specials += rtp_csr
+
+        self.destination = CSRStorage(8)
+        self.hop = CSR(len(rtp_csr.dat_w))
+
+        self.comb += [
+            rtp_csr.adr.eq(self.destination.storage),
+            rtp_csr.dat_w.eq(self.hop.r),
+            rtp_csr.we.eq(self.hop.re),
+            self.hop.w.eq(rtp_csr.dat_r)
+        ]
diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index 75c3fa5e9..9070bf241 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -730,6 +730,8 @@ class _MasterBase(MiniSoC, AMPSoC):
             [self.rtio_core.cri] + self.drtio_cri,
             enable_routing=True)
         self.register_kernel_cpu_csrdevice("cri_con")
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
 
         self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
                                                       self.get_native_sdram_if())
@@ -900,6 +902,8 @@ class _SatelliteBase(BaseSoC):
             [self.local_io.cri] + self.drtio_cri,
             mode="sync", enable_routing=True)
         self.csr_devices.append("cri_con")
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
 
 
 class Master(_MasterBase):