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sayma_rtm_drtio: cleanup (v2.0 only)

This commit is contained in:
Sebastien Bourdeauducq 2019-10-06 16:42:34 +08:00
parent 5612b31860
commit 4198033657
1 changed files with 12 additions and 17 deletions
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29
artiq/gateware/targets/sayma_rtm_drtio.py
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@ -97,15 +97,9 @@ class _SatelliteBase(BaseSoC):
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings) qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll self.submodules += qpll
if self.hw_rev == "v1.0":
drtio_data_pads = platform.request("sata", 0)
elif self.hw_rev == "v2.0":
drtio_data_pads = platform.request("rtm_amc_link", 0)
else:
raise NotImplementedError
self.submodules.drtio_transceiver = gtp_7series.GTP( self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0], qpll_channel=qpll.channels[0],
data_pads=[drtio_data_pads], data_pads=[platform.request("rtm_amc_link", 0)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
@ -137,8 +131,7 @@ class _SatelliteBase(BaseSoC):
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if self.hw_rev == "v2.0": self.comb += platform.request("filtered_clk_sel").eq(1)
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.siphaser = SiPhaser7Series( self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"), si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer, rx_synchronizer=self.rx_synchronizer,
@ -167,9 +160,10 @@ class _SatelliteBase(BaseSoC):
fix_serdes_timing_path(platform) fix_serdes_timing_path(platform)
# HMC clock chip and DAC control # HMC clock chip and DAC control
self.comb += platform.request("ad9154_rst_n", 0).eq(1) self.comb += [
if self.hw_rev == "v2.0": platform.request("ad9154_rst_n", 0).eq(1),
self.comb += platform.request("ad9154_rst_n", 1).eq(1) platform.request("ad9154_rst_n", 1).eq(1)
]
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface( self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
platform.request("hmc_spi"), platform.request("hmc_spi"),
platform.request("ad9154_spi", 0), platform.request("ad9154_spi", 0),
@ -181,16 +175,17 @@ class _SatelliteBase(BaseSoC):
self.submodules.hmc7043_gpo = gpio.GPIOIn( self.submodules.hmc7043_gpo = gpio.GPIOIn(
platform.request("hmc7043_gpo")) platform.request("hmc7043_gpo"))
self.csr_devices.append("hmc7043_gpo") self.csr_devices.append("hmc7043_gpo")
if self.hw_rev == "v2.0":
self.comb += platform.request("hmc830_pwr_en").eq(1)
self.submodules.hmc7043_out_en = gpio.GPIOOut(
platform.request("hmc7043_out_en"))
self.csr_devices.append("hmc7043_out_en")
self.config["HAS_HMC830_7043"] = None self.config["HAS_HMC830_7043"] = None
self.config["CONVERTER_SPI_HMC830_CS"] = 0 self.config["CONVERTER_SPI_HMC830_CS"] = 0
self.config["CONVERTER_SPI_HMC7043_CS"] = 1 self.config["CONVERTER_SPI_HMC7043_CS"] = 1
self.config["HMC830_REF"] = "150" self.config["HMC830_REF"] = "150"
# HMC workarounds
self.comb += platform.request("hmc830_pwr_en").eq(1)
self.submodules.hmc7043_out_en = gpio.GPIOOut(
platform.request("hmc7043_out_en"))
self.csr_devices.append("hmc7043_out_en")
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")