From 41933b88495a3996a898cef7db793fb2e855b650 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Fri, 10 Jan 2025 16:08:30 +0800
Subject: [PATCH] analyzer: revert lookahead buffer

CTI can be inferred by the last signal.
---
 artiq/gateware/rtio/analyzer.py | 57 ++++++++-------------------------
 1 file changed, 13 insertions(+), 44 deletions(-)

diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py
index f301b8a47..294c33e43 100644
--- a/artiq/gateware/rtio/analyzer.py
+++ b/artiq/gateware/rtio/analyzer.py
@@ -151,56 +151,25 @@ class DMAWriter(Module, AutoCSR):
                                        alignment_bits=data_alignment)
         self.byte_count = CSRStatus(64)  # only read when shut down
 
-        layout = [
-            ("data", dw),
-            ("valid_token_count", bits_for(messages_per_dw))
-        ]
-
-        self.sink = stream.Endpoint(layout)
-        self.done = Signal()
+        self.sink = stream.Endpoint(
+            [("data", dw),
+             ("valid_token_count", bits_for(messages_per_dw))])
 
         # # #
 
-        lookahead_buf = stream.Endpoint(layout)
-        buffer_open = Signal()
-
         self.comb += [
-            buffer_open.eq(~lookahead_buf.stb | lookahead_buf.ack),
-            self.sink.ack.eq(buffer_open),
-        ]
-        self.sync += [
-            If(buffer_open,
-                self.sink.connect(lookahead_buf, omit={"ack"}),
-            ),
-        ]
-
-        # RULE 4.30: Set End-Of-Burst to signal the end of the current burst.
-        last = Signal()
-        stale_last = Signal()
-        self.comb += last.eq(lookahead_buf.eop | (lookahead_buf.stb & ~self.sink.stb))
-        self.sync += \
-            If(~buffer_open,
-                If(last, stale_last.eq(1)),
-            ).Else(
-                stale_last.eq(0)
-            )
-        
-        # Write operations completes once EoP is transmitted
-        self.comb += self.done.eq(
-            lookahead_buf.stb & lookahead_buf.ack & lookahead_buf.eop)
-
-        self.comb += [
-            membus.cyc.eq(lookahead_buf.stb),
-            membus.stb.eq(lookahead_buf.stb),
-            membus.cti.eq(Mux(last | stale_last, 0b111, 0b010)),
-            lookahead_buf.ack.eq(membus.ack),
+            membus.cyc.eq(self.sink.stb),
+            membus.stb.eq(self.sink.stb),
+            membus.cti.eq(Mux(self.sink.last, 0b111, 0b010)),
+            self.sink.ack.eq(membus.ack),
             membus.we.eq(1),
-            membus.dat_w.eq(dma.convert_signal(lookahead_buf.data, cpu_dw//8))
+            membus.dat_w.eq(dma.convert_signal(self.sink.data, cpu_dw//8))
         ]
+
         if messages_per_dw > 1:
             for i in range(dw//8):
                 self.comb += membus.sel[i].eq(
-                    lookahead_buf.valid_token_count >= i//(256//8))
+                    self.sink.valid_token_count >= i//(256//8))
         else:
             self.comb += membus.sel.eq(2**(dw//8)-1)
 
@@ -222,7 +191,7 @@ class DMAWriter(Module, AutoCSR):
         self.sync += [
             If(self.reset.re, message_count.eq(0)),
             If(membus.ack, message_count.eq(
-                message_count + lookahead_buf.valid_token_count))
+                message_count + self.sink.valid_token_count))
         ]
 
 
@@ -247,8 +216,8 @@ class Analyzer(Module, AutoCSR):
             enable_r.eq(self.enable.storage),
             If(self.enable.storage & ~enable_r,
                 self.busy.status.eq(1)),
-            If(self.dma.done,
-                self.busy.status.eq(0)),
+            If(self.dma.sink.stb & self.dma.sink.ack & self.dma.sink.eop,
+                self.busy.status.eq(0))
         ]
 
         self.comb += [