diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py
index 9cc7c1559..e4df5b55f 100755
--- a/artiq/gateware/targets/phaser.py
+++ b/artiq/gateware/targets/phaser.py
@@ -224,6 +224,8 @@ class Phaser(MiniSoC, AMPSoC):
         self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
         rtio_channels.append(rtio.LogChannel())
 
+        # TODO: get rid of those bogus DDS defines
+        # currently moninj in the runtime requires them
         self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
         self.config["RTIO_DDS_COUNT"] = 1
         self.config["DDS_CHANNELS_PER_BUS"] = 1