From 407fba232dc10d922d46f218addffb9c158f00c2 Mon Sep 17 00:00:00 2001 From: Marius Weber Date: Fri, 2 Apr 2021 19:50:15 +0100 Subject: [PATCH] Phaser upconverter: set phase-frequency detector to 62.5 MHz (close #1648) The suitable PFD clock depends on the use case and will likely need to be configured by some users. All things being equal, a higher PFD clock is desirable as is results in lower local oscillator phase-noise. Phaser was designed around a maximum PFD clock of 62.5 MHz. In integer mode, with no local oscillator frequency divisor set, a 62.5 MHz PFD clock results in a 125 MHz local oscillator step size. Given the +-200 MHz range of the DUC (more if using the DAC mixer), this step size will be acceptable to many. This seems like the most appropreate default configuration as it should offer the best phase-noise performance. Signed-off-by: Marius Weber --- artiq/coredevice/trf372017.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/artiq/coredevice/trf372017.py b/artiq/coredevice/trf372017.py index d6edb7313..e09d355c2 100644 --- a/artiq/coredevice/trf372017.py +++ b/artiq/coredevice/trf372017.py @@ -4,16 +4,17 @@ class TRF372017: For possible values, documentation, and explanation, see the datasheet. https://www.ti.com/lit/gpn/trf372017 """ - rdiv = 21 # 13b + rdiv = 2 # 13b - highest valid f_PFD ref_inv = 0 neg_vco = 1 icp = 0 # 1.94 mA, 5b icp_double = 0 - cal_clk_sel = 12 # /16, 4b + cal_clk_sel = 0b1110 # div64, 4b - nint = 420 # 16b - pll_div_sel = 0 # /1, 2b - prsc_sel = 1 # 8/9 + # default f_vco is 2.875 GHz + nint = 23 # 16b - lowest value suitable for fractional & integer mode + pll_div_sel = 0b01 # div2, 2b + prsc_sel = 0 # 4/5 vco_sel = 2 # 2b vcosel_mode = 0 cal_acc = 0b00 # 2b @@ -59,8 +60,8 @@ class TRF372017: ioff = 0x80 # 8b qoff = 0x80 # 8b vref_sel = 4 # 0.85 V, 3b - tx_div_sel = 1 # div2, 2b - lo_div_sel = 3 # div8, 2b + tx_div_sel = 0 # div1, 2b + lo_div_sel = 0 # div1, 2b tx_div_bias = 1 # 37.5 µA, 2b lo_div_bias = 2 # 50 µA, 2b