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artiq_ddb_template: mirny_cpld: add refclk, clk_sel args 

Signed-off-by: occheung <occheung@connect.ust.hk>
pull/1563/head
occheung 2020-12-14 12:42:40 +08:00 committed by Sébastien Bourdeauducq
parent 33d39b261a
commit 3f631c417d
1 changed files with 8 additions and 2 deletions
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10
artiq/frontend/artiq_ddb_template.py
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@ -273,9 +273,15 @@ class PeripheralManager:
"type": "local",
"module": "artiq.coredevice.mirny",
"class": "Mirny",
"arguments": {{"spi_device": "spi_{name}"}},
"arguments": {{
"spi_device": "spi_{name}",
"refclk": {refclk},
"clk_sel": {clk_sel}
}},
}}""",
name=mirny_name)
name=mirny_name,
refclk=peripheral.get("refclk", self.master_description.get("rtio_frequency", 125e6)),
clk_sel=peripheral["clk_sel"])
return next(channel)