mirror of https://github.com/m-labs/artiq.git
phaser: nco, settings and init tweaks
This commit is contained in:
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fdb2867757
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3e036e365a
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@ -151,15 +151,17 @@ class Phaser:
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delay(.1*ms) # slack
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# reset
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self.set_cfg(dac_resetb=0, att0_rstn=0, att1_rstn=0)
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self.set_cfg(dac_resetb=0, att0_rstn=0, att1_rstn=0, dac_txena=0)
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self.set_leds(0x00)
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self.set_fan_mu(0)
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self.set_cfg(clk_sel=clk_sel) # bring everything out of reset
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self.set_sync_dly(4) # TODO: tune this?
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self.set_cfg(clk_sel=clk_sel, dac_txena=0) # bring everything out of reset
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# TODO: crossing dac_clk (125 MHz) edges with sync_dly (0-7 ns)
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# should change the optimal fifo_offset
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self.set_sync_dly(4)
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delay(.1*ms) # slack
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# 4 wire SPI, sif4_enable
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self.dac_write(0x02, 0x0082)
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self.dac_write(0x02, 0x0080)
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if self.dac_read(0x7f) != 0x5409:
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raise ValueError("DAC version readback invalid")
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delay(.1*ms)
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@ -168,9 +170,9 @@ class Phaser:
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delay(.1*ms)
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t = self.get_dac_temperature()
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delay(.5*ms)
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if t < 10 or t > 90:
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raise ValueError("DAC temperature out of bounds")
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delay(.5*ms)
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patterns = [
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[0xf05a, 0x05af, 0x5af0, 0xaf05], # test channel/iq/byte/nibble
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@ -182,8 +184,8 @@ class Phaser:
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# either side) and no need to tune at runtime.
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# Parity provides another level of safety.
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for dly in [-2]: # range(-7, 8)
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if dly < 0:
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dly = -dly << 3 # data delay, else clock delay
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if dly < 0: # use data delay, else use clock delay
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dly = -dly << 3
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self.dac_write(0x24, dly << 10)
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for i in range(len(patterns)):
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errors = self.dac_iotest(patterns[i])
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@ -191,38 +193,195 @@ class Phaser:
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raise ValueError("DAC iotest failure")
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delay(.5*ms)
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self.dac_write(0x00, 0x019c) # I=2, fifo, clkdiv_sync, qmc off
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self.dac_write(0x01, 0x040e) # fifo alarms, parity
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self.dac_write(0x02, 0x70a2) # clk alarms, sif4, nco off, mix, mix_gain, 2s
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self.dac_write(0x03, 0xa000) # coarse dac 20.6 mA
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self.dac_write(0x07, 0x40c1) # alarm mask
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self.dac_write(0x09, 0x4000) # fifo_offset
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self.dac_write(0x0d, 0x0000) # fmix, no cmix
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self.dac_write(0x14, 0x5431) # fine nco ab
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self.dac_write(0x15, 0x0323) # coarse nco ab
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self.dac_write(0x16, 0x5431) # fine nco cd
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self.dac_write(0x17, 0x0323) # coarse nco cd
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self.dac_write(0x18, 0x2c60) # P=4, pll run, single cp, pll_ndivsync
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self.dac_write(0x19, 0x8814) # M=16 N=2
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self.dac_write(0x1a, 0xfc00) # pll_vco=63, 4 GHz
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delay(.2*ms) # slack
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self.dac_write(0x1b, 0x0800) # int ref, fuse
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self.dac_write(0x1e, 0x9999) # qmc sync from sif and reg
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self.dac_write(0x1f, 0x9982) # mix sync, nco sync, istr is istr, sif_sync
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self.dac_write(0x20, 0x2400) # fifo sync ISTR-OSTR
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self.dac_write(0x22, 0x1be4) # reverse dacs for spectral inversion and layout
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self.dac_write(0x24, 0x0000) # clk and data delays
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qmc_corr_ena = 0 # msb ab
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qmc_offset_ena = 0 # msb ab
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invsinc_ena = 0 # msb ab
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interpolation = 1 # 2x
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fifo_ena = 1
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alarm_out_ena = 1
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alarm_out_pol = 1
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clkdiv_sync_ena = 1
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self.dac_write(0x00,
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(qmc_offset_ena << 14) | (qmc_corr_ena << 12) |
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(interpolation << 8) | (fifo_ena << 7) |
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(alarm_out_ena << 4) | (alarm_out_pol << 3) |
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(clkdiv_sync_ena << 2) | (invsinc_ena << 0))
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iotest_ena = 0
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cnt64_ena = 0
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oddeven_parity = 0 # even
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single_parity_ena = 1
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dual_parity_ena = 0
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rev_interface = 0
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dac_complement = 0b0000 # msb A
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alarm_fifo = 0b111 # msb 2-away
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self.dac_write(0x01,
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(iotest_ena << 15) | (cnt64_ena << 12) |
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(oddeven_parity << 11) | (single_parity_ena << 10) |
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(dual_parity_ena << 9) | (rev_interface << 8) |
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(dac_complement << 4) | (alarm_fifo << 1))
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dacclkgone_ena = 1
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dataclkgone_ena = 1
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collisiongone_ena = 1
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sif4_ena = 1
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mixer_ena = 0
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mixer_gain = 1
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nco_ena = 0
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revbus = 0
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twos = 1
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self.dac_write(0x02,
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(dacclkgone_ena << 14) | (dataclkgone_ena << 13) |
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(collisiongone_ena << 12) | (sif4_ena << 7) |
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(mixer_ena << 6) | (mixer_gain << 5) |
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(nco_ena << 4) | (revbus << 3) | (twos << 1))
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coarse_dac = 0xa # 20.6 mA, 0-15
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sif_txenable = 0
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self.dac_write(0x03, (coarse_dac << 12) | (sif_txenable << 0))
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mask_alarm_from_zerochk = 0
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mask_alarm_fifo_collision = 0
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mask_alarm_fifo_1away = 0
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mask_alarm_fifo_2away = 0
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mask_alarm_dacclk_gone = 0
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mask_alarm_dataclk_gone = 0
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mask_alarm_output_gone = 0
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mask_alarm_from_iotest = 0
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mask_alarm_from_pll = 0
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mask_alarm_parity = 0b0000 # msb a
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self.dac_write(0x07,
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(mask_alarm_from_zerochk << 15) | (1 << 14) |
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(mask_alarm_fifo_collision << 13) | (mask_alarm_fifo_1away << 12) |
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(mask_alarm_fifo_2away << 11) | (mask_alarm_dacclk_gone << 10) |
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(mask_alarm_dataclk_gone << 9) | (mask_alarm_output_gone << 8) |
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(mask_alarm_from_iotest << 7) | (1 << 6) |
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(mask_alarm_from_pll << 5) | (mask_alarm_parity << 1))
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qmc_offseta = 0 # 12b
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self.dac_write(0x08, qmc_offseta)
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fifo_offset = 2 # 0-7
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qmc_offsetb = 0 # 12b
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self.dac_write(0x09, (fifo_offset << 13) | qmc_offsetb)
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qmc_offsetc = 0 # 12b
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self.dac_write(0x0a, qmc_offsetc)
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qmc_offsetd = 0 # 12b
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self.dac_write(0x0b, qmc_offsetd)
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qmc_gaina = 0 # 11b
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self.dac_write(0x0c, qmc_gaina)
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cmix_fs8 = 0
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cmix_fs4 = 0
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cmix_fs2 = 0
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cmix_nfs4 = 0
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qmc_gainb = 0 # 11b
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self.dac_write(0x0d,
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(cmix_fs8 << 15) | (cmix_fs4 << 14) | (cmix_fs2 << 12) |
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(cmix_nfs4 << 11) | qmc_gainb)
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qmc_gainc = 0 # 11b
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self.dac_write(0x0e, qmc_gainc)
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output_delayab = 0b00
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output_delaycd = 0b00
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qmc_gaind = 0 # 11b
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self.dac_write(0x0f, (output_delayab << 14) | (output_delaycd << 12) |
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qmc_gaind)
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qmc_phaseab = 0 # 12b
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self.dac_write(0x10, qmc_phaseab)
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qmc_phasecd = 0 # 12b
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self.dac_write(0x11, qmc_phasecd)
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pll_reset = 0
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pll_ndivsync_ena = 1
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pll_ena = 1
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pll_cp = 0b01 # single charge pump
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pll_p = 0b100 # p=4
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self.dac_write(0x18,
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(0b001 << 13) | (pll_reset << 12) |
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(pll_ndivsync_ena << 11) | (pll_ena << 10) |
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(pll_cp << 6) | (pll_p << 3))
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pll_m2 = 1 # x2
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pll_m = 8 # m = 8
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pll_n = 0b0001 # n = 2
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pll_vcotune = 0b01
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self.dac_write(0x19,
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(pll_m2 << 15) | (pll_m << 8) | (pll_n << 4) | (pll_vcotune << 2))
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delay(.5*ms) # slack
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pll_vco = 0x3f # 4 GHz
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bias_sleep = 0
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tsense_sleep = 0
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pll_sleep = 0
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clkrecv_sleep = 0
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dac_sleep = 0b0000 # msb a
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self.dac_write(0x1a,
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(pll_vco << 10) | (bias_sleep << 7) | (tsense_sleep << 6) |
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(pll_sleep << 5) | (clkrecv_sleep << 4) | (dac_sleep << 0))
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extref_ena = 0
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fuse_sleep = 1
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atest = 0b00000 # atest mode
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self.dac_write(0x1b,
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(extref_ena << 15) | (fuse_sleep << 11) | (atest << 0))
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syncsel_qmcoffsetab = 0b1001 # sif_sync and register write
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syncsel_qmcoffsetcd = 0b1001 # sif_sync and register write
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syncsel_qmccorrab = 0b1001 # sif_sync and register write
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syncsel_qmccorrcd = 0b1001 # sif_sync and register write
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self.dac_write(0x1e,
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(syncsel_qmcoffsetab << 12) | (syncsel_qmcoffsetcd << 8) |
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(syncsel_qmccorrab << 4) | (syncsel_qmccorrcd << 0))
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syncsel_mixerab = 0b1001 # sif_sync and register write
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syncsel_mixercd = 0b1001 # sif_sync and register write
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syncsel_nco = 0b1000 # sif_sync
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syncsel_fifo_input = 0b10 # external lvds istr
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sif_sync = 1
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self.dac_write(0x1e,
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(syncsel_mixerab << 12) | (syncsel_mixercd << 8) |
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(syncsel_nco << 4) | (syncsel_fifo_input << 2) |
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(sif_sync << 1))
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syncsel_fifoin = 0b0010 # istr
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syncsel_fifoout = 0b0100 # ostr
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clkdiv_sync_sel = 0 # ostr
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self.dac_write(0x20,
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(syncsel_fifoin << 12) | (syncsel_fifoout << 8) |
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(clkdiv_sync_sel << 0))
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path_a_sel = 0b00
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path_b_sel = 0b01
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path_c_sel = 0b10
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path_d_sel = 0b11
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# reverse dacs (DCBA) for spectral inversion and layout
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dac_a_sel = 0b11
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dac_b_sel = 0b10
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dac_c_sel = 0b01
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dac_d_sel = 0b00
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self.dac_write(0x22,
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(path_a_sel << 14) | (path_b_sel << 12) |
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(path_c_sel << 10) | (path_d_sel << 8) |
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(dac_a_sel << 6) | (dac_b_sel << 4) |
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(dac_c_sel << 2) | (dac_d_sel << 0))
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dac_sleep_en = 0b1111 # msb a
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clkrecv_sleep_en = 1
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pll_sleep_en = 1
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lvds_data_sleep_en = 1
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lvds_control_sleep_en = 1
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temp_sense_sleep_en = 1
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bias_sleep_en = 1
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self.dac_write(0x23,
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(dac_sleep_en << 12) | (clkrecv_sleep_en << 11) |
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(pll_sleep_en << 10) | (lvds_data_sleep_en << 9) |
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(lvds_control_sleep_en << 8) | (temp_sense_sleep_en << 7) |
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(1 << 6) | (bias_sleep_en << 5) | (0x1f << 0))
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# self.dac_write(0x24, 0x0000) # clk and data delays (tuned above)
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ostrtodig_sel = 0
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ramp_ena = 0
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sifdac_ena = 0
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self.dac_write(0x2d,
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(ostrtodig_sel << 14) | (ramp_ena << 13) | (0x002 << 1) |
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(sifdac_ena << 0))
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grp_delaya = 0x00
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grp_delayb = 0x00
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self.dac_write(0x2e, (grp_delaya << 8) | (grp_delayb << 0))
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grp_delayc = 0x00
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grp_delayd = 0x00
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self.dac_write(0x2f, (grp_delayc << 8) | (grp_delayd << 0))
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sifdac = 0
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self.dac_write(0x30, sifdac)
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delay(2*ms) # lock pll
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lvolt = self.dac_read(0x18) & 7
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delay(.1*ms)
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if lvolt < 2 or lvolt > 5:
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raise ValueError("DAC PLL tuning voltage out of bounds")
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self.clear_dac_alarms()
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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has_upconverter = hw_rev & PHASER_HW_REV_VARIANT
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delay(.1*ms) # slack
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for ch in range(2):
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channel = self.channel[ch]
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@ -233,38 +392,43 @@ class Phaser:
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delay(.1*ms)
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channel.set_att(31.5*dB)
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# test oscillators and DUC
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for i in range(len(channel.oscillator)):
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oscillator = channel.oscillator[i]
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asf = 0
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if i == 0:
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asf = 0x7fff
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else:
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asf = 0
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# pi/4 phase
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oscillator.set_amplitude_phase_mu(asf=asf, pow=0x2000, clr=1)
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# 6pi/4 phase
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oscillator.set_amplitude_phase_mu(asf=asf, pow=0xc000, clr=1)
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delay_mu(8)
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delay(1*us) # settle link, pipeline and impulse response
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# test oscillator and DUC and their phase sign
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channel.set_duc_phase_mu(0)
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# 3pi/4
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channel.set_duc_phase_mu(0x6000)
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channel.set_duc_cfg(select=0, clr=1)
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self.duc_stb()
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delay(.1*ms) # settle link, pipeline and impulse response
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data = channel.get_dac_data()
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delay(.1*ms)
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if data != 0x4a124a12:
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sqrt2 = 0x5a81 # 0x7fff/sqrt(2)
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data_i = data & 0xffff
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data_q = (data >> 16) & 0xffff
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# allow ripple
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if (data_i < sqrt2 - 30 or data_i > sqrt2 or
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abs(data_i - data_q) > 2):
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print(data)
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raise ValueError("DUC+oscillator phase/amplitude test failed")
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# self.dac_write(0x20, 0x0000) # stop fifo sync
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# alarm = self.get_sta() & 1
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# delay(.1*ms)
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self.clear_dac_alarms()
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delay(2*ms) # let it run a bit
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self.check_dac_alarms()
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@kernel
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def check_dac_alarms(self):
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alarm = self.get_dac_alarms()
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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has_upconverter = hw_rev & PHASER_HW_REV_VARIANT
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delay(.1*ms) # slack
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if alarm & ~0x0040: # ignore PLL alarms (see DS)
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print(alarm)
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raise ValueError("DAC alarm")
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self.set_cfg(clk_sel=clk_sel) # txena
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@kernel
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def write8(self, addr, data):
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@ -493,6 +657,14 @@ class Phaser:
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"""
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return self.dac_read(0x05)
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@kernel
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def check_dac_alarms(self):
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alarm = self.get_dac_alarms()
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delay(.1*ms) # slack
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if alarm & ~0x0040: # ignore PLL alarms (see DS)
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print(alarm)
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raise ValueError("DAC alarm")
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@kernel
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def clear_dac_alarms(self):
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"""Clear DAC alarm flags."""
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@ -542,6 +714,17 @@ class Phaser:
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class PhaserChannel:
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"""Phaser channel IQ pair.
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A Phaser channel contains:
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* multiple oscillators (in the coredevice phy),
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* an interpolation chain and digital upconverter (DUC) on Phaser,
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* several channel-specific settings in the DAC:
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* quadrature modulation compensation QMC
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* numerically controlled oscillator NCO or coarse mixer CMIX,
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* the analog quadrature upconverter (in the Phaser-Upconverter hardware
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variant), and
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* a digitally controlled step attenuator.
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Attributes:
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* :attr:`oscillator`: List of five :class:`PhaserOscillator`.
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@ -636,6 +819,42 @@ class PhaserChannel:
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pow = int32(round(phase*(1 << 16)))
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self.set_duc_phase_mu(pow)
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@kernel
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def set_nco_frequency_mu(self, ftw):
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"""Set the NCO frequency.
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:param ftw: NCO frequency tuning word (32 bit)
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"""
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self.phaser.dac_write(0x15 + (self.index << 1), ftw >> 16)
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self.phaser.dac_write(0x14 + (self.index << 1), ftw)
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@kernel
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def set_nco_frequency(self, frequency):
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"""Set the NCO frequency in SI units.
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:param frequency: NCO frequency in Hz (passband from -400 MHz
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to 400 MHz, wrapping around at +- 500 MHz)
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"""
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||||
ftw = int32(round(frequency*((1 << 31)/(500*MHz))))
|
||||
self.set_nco_frequency_mu(ftw)
|
||||
|
||||
@kernel
|
||||
def set_nco_phase_mu(self, pow):
|
||||
"""Set the NCO phase offset.
|
||||
|
||||
:param pow: NCO phase offset word (16 bit)
|
||||
"""
|
||||
self.phaser.dac_write(0x12 + self.index, pow)
|
||||
|
||||
@kernel
|
||||
def set_nco_phase(self, phase):
|
||||
"""Set the NCO phase in SI units.
|
||||
|
||||
:param phase: NCO phase in turns
|
||||
"""
|
||||
pow = int32(round(phase*(1 << 16)))
|
||||
self.set_duc_phase_mu(pow)
|
||||
|
||||
@kernel
|
||||
def set_att_mu(self, data):
|
||||
"""Set channel attenuation.
|
||||
|
|
|
|||
Loading…
Reference in New Issue