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drtio: add packet counters
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parent
747da3da15
commit
3da1cce783
artiq/gateware/drtio
@ -25,6 +25,10 @@ class _CSRs(AutoCSR):
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self.err_present = CSR()
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self.err_present = CSR()
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self.err_code = CSRStatus(8)
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self.err_code = CSRStatus(8)
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self.dbg_update_packet_cnt = CSR()
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self.dbg_packet_cnt_tx = CSRStatus(32)
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self.dbg_packet_cnt_rx = CSRStatus(32)
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class RTController(Module):
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class RTController(Module):
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def __init__(self, rt_packets, channel_count, fine_ts_width):
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def __init__(self, rt_packets, channel_count, fine_ts_width):
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@ -156,6 +160,7 @@ class RTController(Module):
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)
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)
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)
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)
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# channel state access
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self.comb += [
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self.comb += [
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self.csrs.o_dbg_fifo_space.status.eq(fifo_spaces.dat_r),
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self.csrs.o_dbg_fifo_space.status.eq(fifo_spaces.dat_r),
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self.csrs.o_dbg_last_timestamp.status.eq(last_timestamps.dat_r),
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self.csrs.o_dbg_last_timestamp.status.eq(last_timestamps.dat_r),
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@ -167,12 +172,20 @@ class RTController(Module):
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)
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)
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]
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]
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# errors
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self.comb += [
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self.comb += [
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self.csrs.err_present.w.eq(rt_packets.error_not),
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self.csrs.err_present.w.eq(rt_packets.error_not),
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rt_packets.error_not_ack.eq(self.csrs.err_present.re),
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rt_packets.error_not_ack.eq(self.csrs.err_present.re),
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self.csrs.err_code.status.eq(rt_packets.error_code)
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self.csrs.err_code.status.eq(rt_packets.error_code)
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]
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]
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# packet counters
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self.sync += \
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If(self.csrs.dbg_update_packet_cnt.re,
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self.csrs.dbg_packet_cnt_tx.status.eq(rt_packets.packet_cnt_tx),
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self.csrs.dbg_packet_cnt_rx.status.eq(rt_packets.packet_cnt_rx)
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)
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def get_kernel_csrs(self):
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def get_kernel_csrs(self):
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return self.kcsrs.get_csrs()
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return self.kcsrs.get_csrs()
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@ -5,6 +5,8 @@ from migen.genlib.fsm import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.cdc import PulseSynchronizer
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from migen.genlib.cdc import PulseSynchronizer
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from artiq.gateware.rtio.cdc import GrayCodeTransfer
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def layout_len(l):
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def layout_len(l):
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return sum(e[1] for e in l)
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return sum(e[1] for e in l)
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@ -404,6 +406,10 @@ class RTPacketMaster(Module):
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self.error_not_ack = Signal()
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self.error_not_ack = Signal()
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self.error_code = Signal(8)
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self.error_code = Signal(8)
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# packet counters
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self.packet_cnt_tx = Signal(32)
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self.packet_cnt_rx = Signal(32)
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# # #
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# # #
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# CDC
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# CDC
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@ -545,3 +551,33 @@ class RTPacketMaster(Module):
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fifo_space.eq(rx_dp.packet_as["fifo_space_reply"].space),
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fifo_space.eq(rx_dp.packet_as["fifo_space_reply"].space),
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NextState("INPUT")
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NextState("INPUT")
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)
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)
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# packet counters
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tx_frame_r = Signal()
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packet_cnt_tx = Signal(32)
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self.sync.rtio += [
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tx_frame_r.eq(link_layer.tx_rt_frame),
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If(link_layer.tx_rt_frame & ~tx_frame_r,
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packet_cnt_tx.eq(packet_cnt_tx + 1))
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]
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cdc_packet_cnt_tx = GrayCodeTransfer(32)
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self.submodules += cdc_packet_cnt_tx
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self.comb += [
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cdc_packet_cnt_tx.i.eq(packet_cnt_tx),
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self.packet_cnt_tx.eq(cdc_packet_cnt_tx.o)
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]
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rx_frame_r = Signal()
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packet_cnt_rx = Signal(32)
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self.sync.rtio_rx += [
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rx_frame_r.eq(link_layer.rx_rt_frame),
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If(link_layer.rx_rt_frame & ~rx_frame_r,
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packet_cnt_rx.eq(packet_cnt_rx + 1))
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]
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cdc_packet_cnt_rx = ClockDomainsRenamer({"rtio": "rtio_rx"})(
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GrayCodeTransfer(32))
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self.submodules += cdc_packet_cnt_rx
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self.comb += [
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cdc_packet_cnt_rx.i.eq(packet_cnt_rx),
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self.packet_cnt_rx.eq(cdc_packet_cnt_rx.o)
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]
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