mirror of https://github.com/m-labs/artiq.git
parent
f2632e0fd1
commit
3cbbcdfe96
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@ -17,7 +17,8 @@ class Channel(_ChannelPHY):
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self.phys = []
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cfg = self.i[0]
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rl = rtlink.Interface(rtlink.OInterface(
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data_width=len(cfg.data), address_width=len(cfg.addr)))
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data_width=len(cfg.data), address_width=len(cfg.addr),
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enable_replace=False))
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self.comb += [
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cfg.stb.eq(rl.o.stb),
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rl.o.busy.eq(~cfg.ack),
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