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gateware/nist_clock: increase DDS bus drive strength. Closes #468

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Sebastien Bourdeauducq 2016-06-07 11:08:05 -04:00
parent e47538ca33
commit 3bd190e624
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/nist_clock.py
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@ -36,7 +36,7 @@ fmc_adapter_io = [
Subsignal("wr_n", Pins("LPC:LA24_P")), Subsignal("wr_n", Pins("LPC:LA24_P")),
Subsignal("rd_n", Pins("LPC:LA25_N")), Subsignal("rd_n", Pins("LPC:LA25_N")),
Subsignal("rst", Pins("LPC:LA25_P")), Subsignal("rst", Pins("LPC:LA25_P")),
IOStandard("LVTTL")), IOStandard("LVTTL"), Misc("DRIVE=24")),
("i2c_fmc", 0, ("i2c_fmc", 0,
Subsignal("scl", Pins("LPC:IIC_SCL")), Subsignal("scl", Pins("LPC:IIC_SCL")),