mirror of https://github.com/m-labs/artiq.git
test/fir: look at overshoot behavior
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@ -22,17 +22,23 @@ class Transfer(Module):
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yield
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yield
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yi[:] = (yield from [(yield o) for o in self.dut.o])
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yi[:] = (yield from [(yield o) for o in self.dut.o])
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def run(self, samples, amplitude=1.):
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def run(self, samples, amplitude=1., seed=None):
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if seed is not None:
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np.random.seed(seed)
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w = 2**(self.dut.width - 1) - 1
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w = 2**(self.dut.width - 1) - 1
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x = np.round(np.random.uniform(
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x = np.round(np.random.uniform(
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-amplitude*w, amplitude*w, samples))
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-amplitude*w, amplitude*w, samples))
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y = np.empty_like(x)
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y = self.run_data(x)
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run_simulation(self, [self.drive(x), self.record(y)],
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vcd_name="fir.vcd")
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x /= w
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x /= w
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y /= w
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y /= w
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return x, y
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return x, y
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def run_data(self, x):
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y = np.empty_like(x)
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run_simulation(self, [self.drive(x), self.record(y)],
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vcd_name="fir.vcd")
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return y
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def analyze(self, x, y):
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def analyze(self, x, y):
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fig, ax = plt.subplots(3)
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fig, ax = plt.subplots(3)
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ax[0].plot(x, "c-.", label="input")
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ax[0].plot(x, "c-.", label="input")
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@ -81,7 +87,7 @@ class UpTransfer(Transfer):
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def _main():
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def _main():
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if True:
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if True:
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coeff = fir.halfgen4_cascade(8, width=.4, order=8)
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coeff = fir.halfgen4_cascade(2, width=.4, order=8)
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dut = fir.ParallelHBFUpsampler(coeff, width=16)
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dut = fir.ParallelHBFUpsampler(coeff, width=16)
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# print(verilog.convert(dut, ios=set([dut.i] + dut.o)))
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# print(verilog.convert(dut, ios=set([dut.i] + dut.o)))
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tb = UpTransfer(dut)
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tb = UpTransfer(dut)
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@ -91,7 +97,13 @@ def _main():
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# print(verilog.convert(dut, ios=set(dut.i + dut.o)))
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# print(verilog.convert(dut, ios=set(dut.i + dut.o)))
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tb = Transfer(dut)
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tb = Transfer(dut)
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x, y = tb.run(samples=1 << 10, amplitude=.5)
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if True:
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x, y = tb.run(samples=1 << 10, amplitude=.5, seed=0x1234567)
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else:
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x = np.zeros(100)
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x[:50] = 1 << 8
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x[50:] = 1 << 13
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y = tb.run_data(x)
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tb.analyze(x, y)
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tb.analyze(x, y)
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plt.show()
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plt.show()
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