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test/full_stack: style and add note about loopback test connections
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@ -7,7 +7,7 @@ from artiq.coredevice import comm_serial, core, runtime_exceptions, rtio
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from artiq.sim import devices as sim_devices
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NO_HARDWARE = bool(os.getenv("ARTIQ_NO_HARDWARE"))
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no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE"))
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def _run_on_device(k_class, **parameters):
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@ -136,7 +136,7 @@ class _Exceptions(AutoContext):
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self.trace.append(104)
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@unittest.skipIf(NO_HARDWARE, "no hardware")
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@unittest.skipIf(no_hardware, "no hardware")
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class ExecutionCase(unittest.TestCase):
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def test_primes(self):
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l_device, l_host = [], []
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@ -208,8 +208,10 @@ class _RTIOSequenceError(AutoContext):
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self.o.pulse(25*us)
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@unittest.skipIf(NO_HARDWARE, "no hardware")
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@unittest.skipIf(no_hardware, "no hardware")
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class RTIOCase(unittest.TestCase):
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# Connect channels 0 and 1 together for this test
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# (C11 and C13 on Papilio Pro)
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def test_loopback(self):
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npulses = 4
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with comm_serial.Comm() as comm:
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