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test/full_stack: style and add note about loopback test connections

This commit is contained in:
Sebastien Bourdeauducq 2014-11-07 14:15:40 -08:00
parent 62677ed660
commit 391ff10345
1 changed files with 5 additions and 3 deletions
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8
test/full_stack.py
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@ -7,7 +7,7 @@ from artiq.coredevice import comm_serial, core, runtime_exceptions, rtio
from artiq.sim import devices as sim_devices
NO_HARDWARE = bool(os.getenv("ARTIQ_NO_HARDWARE"))
no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE"))
def _run_on_device(k_class, **parameters):
@ -136,7 +136,7 @@ class _Exceptions(AutoContext):
self.trace.append(104)
@unittest.skipIf(NO_HARDWARE, "no hardware")
@unittest.skipIf(no_hardware, "no hardware")
class ExecutionCase(unittest.TestCase):
def test_primes(self):
l_device, l_host = [], []
@ -208,8 +208,10 @@ class _RTIOSequenceError(AutoContext):
self.o.pulse(25*us)
@unittest.skipIf(NO_HARDWARE, "no hardware")
@unittest.skipIf(no_hardware, "no hardware")
class RTIOCase(unittest.TestCase):
# Connect channels 0 and 1 together for this test
# (C11 and C13 on Papilio Pro)
def test_loopback(self):
npulses = 4
with comm_serial.Comm() as comm: