gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache

artiq/gateware/amp/kernel_cpu.py

@@ -3,12 +3,11 @@ from migen.bank.description import *
 from migen.bus import wishbone
 
 from misoclib.cpu import mor1kx
-from misoclib.mem.sdram.frontend.wishbone2lasmi import WB2LASMI
 from misoclib.soc import mem_decoder
 
 
 class KernelCPU(Module):
-    def __init__(self, platform, lasmim,
+    def __init__(self, platform,
                  exec_address=0x40400000,
                  main_mem_origin=0x40000000,
                  l2_size=8192):
@@ -29,16 +28,8 @@ class KernelCPU(Module):
             "sys_kernel")
 
         # DRAM access
-        # XXX Vivado 2014.X workaround
-        from mibuild.xilinx.vivado import XilinxVivadoToolchain
-        if isinstance(platform.toolchain, XilinxVivadoToolchain):
-            from migen.fhdl.simplify import FullMemoryWE
-            self.submodules.wishbone2lasmi = FullMemoryWE()(
-                WB2LASMI(l2_size//4, lasmim))
-        else:
-            self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
-        self.add_wb_slave(mem_decoder(main_mem_origin),
-                          self.wishbone2lasmi.wishbone)
+        self.wb_sdram = wishbone.Interface()
+        self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
 
     def get_csrs(self):
         return [self._reset]

artiq/gateware/soc.py

@@ -19,8 +19,9 @@ class AMPSoC:
 
         self.submodules.timer0 = timer.Timer(width=64)
 
-        self.submodules.kernel_cpu = amp.KernelCPU(
-            self.platform, self.sdram.crossbar.get_master())
+        self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
+        self.add_wb_sdram_if(self.kernel_cpu.wb_sdram)
+
         self.submodules.mailbox = amp.Mailbox()
         self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
                           self.mailbox.i1)

soc/targets/artiq_kc705.py

@@ -6,6 +6,7 @@ from mibuild.xilinx.vivado import XilinxVivadoToolchain
 
 from misoclib.com import gpio
 from misoclib.soc import mem_decoder
+from misoclib.mem.sdram.core.minicon import MiniconSettings
 from targets.kc705 import MiniSoC
 
 from artiq.gateware.soc import AMPSoC
@@ -48,7 +49,9 @@ class NIST_QC1(MiniSoC, AMPSoC):
 
     def __init__(self, platform, cpu_type="or1k", **kwargs):
         MiniSoC.__init__(self, platform,
-                         cpu_type=cpu_type, with_timer=False, **kwargs)
+                         cpu_type=cpu_type,
+                         sdram_controller_settings=MiniconSettings(l2_size=128*1024),
+                         with_timer=False, **kwargs)
         AMPSoC.__init__(self)
         platform.add_extension(nist_qc1.fmc_adapter_io)
 

soc/targets/artiq_pipistrello.py

@@ -4,6 +4,7 @@ from migen.bank import wbgen
 
 from misoclib.com import gpio
 from misoclib.soc import mem_decoder
+from misoclib.mem.sdram.core.minicon import MiniconSettings
 from targets.pipistrello import BaseSoC
 
 from artiq.gateware.soc import AMPSoC
@@ -69,7 +70,9 @@ class NIST_QC1(BaseSoC, AMPSoC):
 
     def __init__(self, platform, cpu_type="or1k", **kwargs):
         BaseSoC.__init__(self, platform,
-                         cpu_type=cpu_type, with_timer=False, **kwargs)
+                         cpu_type=cpu_type,
+                         sdram_controller_settings=MiniconSettings(l2_size=128*1024),
+                         with_timer=False, **kwargs)
         AMPSoC.__init__(self)
         platform.toolchain.ise_commands += """
 trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf