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ad9912: support configurable clk_div
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2bea5e3d58
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@ -21,14 +21,14 @@ class AD9912:
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:param sw_device: Name of the RF switch device. The RF switch is a
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TTLOut channel available as the :attr:`sw` attribute of this instance.
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:param pll_n: DDS PLL multiplier. The DDS sample clock is
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f_ref*pll_n where f_ref is the reference frequency (set in the parent
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Urukul CPLD instance).
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f_ref/clk_div*pll_n where f_ref is the reference frequency and clk_div
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is the reference clock divider (both set in the parent Urukul CPLD
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instance).
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus",
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"ftw_per_hz", "sysclk", "pll_n"}
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kernel_invariants = {"chip_select", "cpld", "core", "bus", "ftw_per_hz"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=10):
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pll_n=10):
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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@ -38,9 +38,9 @@ class AD9912:
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self.sw = dmgr.get(sw_device)
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self.kernel_invariants.add("sw")
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self.pll_n = pll_n
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self.sysclk = self.cpld.refclk*pll_n
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assert self.sysclk <= 1e9
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self.ftw_per_hz = 1/self.sysclk*(int64(1) << 48)
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sysclk = self.cpld.refclk/[1, 1, 2, 4][self.cpld.clk_div]*pll_n
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assert sysclk <= 1e9
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self.ftw_per_hz = 1/sysclk*(int64(1) << 48)
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@kernel
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def write(self, addr, data, length):
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