spi: register clk

following m-labs/misoc#65 1dc68b0d0b
2017-12-28 16:49:35 +01:00 · 2017-12-28 16:49:35 +01:00 · 37f9c0b10c
parent 3505878176
commit 37f9c0b10c
1 changed files with 5 additions and 1 deletions
--- a/artiq/gateware/spi.py
+++ b/artiq/gateware/spi.py
@ -203,7 +203,11 @@ class SPIMaster(Module):
            mosi_oe.eq(
                ~config.offline & spi.cs &
                (spi.oe | ~config.half_duplex)),
-            clk.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity)
+        ]
+        self.sync += [
+            If(spi.cg.ce & spi.cg.edge,
+                clk.eq((~spi.cg.clk & spi.cs_next) ^ config.clk_polarity)
+            )
        ]

        if pads_n is None: