mirror of https://github.com/m-labs/artiq.git
sayma: RF switch control is active-low on Basemod, invert
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@ -4,7 +4,7 @@ from artiq.gateware.rtio.phy import ttl_serdes_generic
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class _OSERDESE2_8X(Module):
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def __init__(self, pad, pad_n=None):
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def __init__(self, pad, pad_n=None, invert=False):
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self.o = Signal(8)
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self.t_in = Signal()
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self.t_out = Signal()
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@ -16,12 +16,13 @@ class _OSERDESE2_8X(Module):
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self.specials += Instance("OSERDESE2",
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p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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p_INIT_OQ=0b11111111 if invert else 0b00000000,
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o_OQ=pad_o, o_TQ=self.t_out,
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i_RST=ResetSignal("rio_phy"),
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i_CLK=ClockSignal("rtiox4"),
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i_CLKDIV=ClockSignal("rio_phy"),
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i_D1=o[0], i_D2=o[1], i_D3=o[2], i_D4=o[3],
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i_D5=o[4], i_D6=o[5], i_D7=o[6], i_D8=o[7],
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i_D1=o[0] ^ invert, i_D2=o[1] ^ invert, i_D3=o[2] ^ invert, i_D4=o[3] ^ invert,
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i_D5=o[4] ^ invert, i_D6=o[5] ^ invert, i_D7=o[6] ^ invert, i_D8=o[7] ^ invert,
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i_TCE=1, i_OCE=1,
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i_T1=self.t_in)
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if pad_n is None:
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@ -106,8 +107,8 @@ class _IOSERDESE2_8X(Module):
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class Output_8X(ttl_serdes_generic.Output):
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def __init__(self, pad, pad_n=None):
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serdes = _OSERDESE2_8X(pad, pad_n)
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def __init__(self, pad, pad_n=None, invert=False):
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serdes = _OSERDESE2_8X(pad, pad_n, invert=invert)
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self.submodules += serdes
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ttl_serdes_generic.Output.__init__(self, serdes)
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@ -180,7 +180,8 @@ class Satellite(_SatelliteBase):
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print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}"
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.format(bm, len(rtio_channels)))
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for i in range(4):
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phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i))
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phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i),
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invert=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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