From 37bd0c2566f76bf6fbd7f53eca72ad9f46eda362 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 18 May 2018 16:15:07 +0800 Subject: [PATCH] kasli: add USTC target --- artiq/examples/kasli_ustc/device_db.py | 189 +++++++++++++++++++ artiq/examples/kasli_ustc/repository/demo.py | 82 ++++++++ artiq/frontend/artiq_flash.py | 3 +- artiq/gateware/targets/kasli.py | 68 ++++++- 4 files changed, 339 insertions(+), 3 deletions(-) create mode 100644 artiq/examples/kasli_ustc/device_db.py create mode 100644 artiq/examples/kasli_ustc/repository/demo.py diff --git a/artiq/examples/kasli_ustc/device_db.py b/artiq/examples/kasli_ustc/device_db.py new file mode 100644 index 000000000..31b1bf03d --- /dev/null +++ b/artiq/examples/kasli_ustc/device_db.py @@ -0,0 +1,189 @@ +core_addr = "kasli-2.lab.m-labs.hk" + +device_db = { + "core": { + "type": "local", + "module": "artiq.coredevice.core", + "class": "Core", + "arguments": {"host": core_addr, "ref_period": 1e-9} + }, + "core_log": { + "type": "controller", + "host": "::1", + "port": 1068, + "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr + }, + "core_cache": { + "type": "local", + "module": "artiq.coredevice.cache", + "class": "CoreCache" + }, + "core_dma": { + "type": "local", + "module": "artiq.coredevice.dma", + "class": "CoreDMA" + }, + + "i2c_switch0": { + "type": "local", + "module": "artiq.coredevice.i2c", + "class": "PCA9548", + "arguments": {"address": 0xe0} + }, + "i2c_switch1": { + "type": "local", + "module": "artiq.coredevice.i2c", + "class": "PCA9548", + "arguments": {"address": 0xe2} + }, +} + +for i in range(24): + device_db["ttl" + str(i)] = { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLInOut" if i < 4 else "TTLOut", + "arguments": {"channel": i}, + } + +device_db.update( + spi_urukul0={ + "type": "local", + "module": "artiq.coredevice.spi2", + "class": "SPIMaster", + "arguments": {"channel": 24} + }, + ttl_urukul0_io_update={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 25} + }, + ttl_urukul0_sw0={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 26} + }, + ttl_urukul0_sw1={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 27} + }, + ttl_urukul0_sw2={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 28} + }, + ttl_urukul0_sw3={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 29} + }, + urukul0_cpld={ + "type": "local", + "module": "artiq.coredevice.urukul", + "class": "CPLD", + "arguments": { + "spi_device": "spi_urukul0", + "io_update_device": "ttl_urukul0_io_update", + "refclk": 125e6, + "clk_sel": 0 + } + } +) + +for i in range(4): + device_db["urukul0_ch" + str(i)] = { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 4 + i, + "cpld_device": "urukul0_cpld", + "sw_device": "ttl_urukul0_sw" + str(i) + } + } + + +device_db.update( + spi_urukul1={ + "type": "local", + "module": "artiq.coredevice.spi2", + "class": "SPIMaster", + "arguments": {"channel": 30} + }, + ttl_urukul1_io_update={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 31} + }, + ttl_urukul1_sw0={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 32} + }, + ttl_urukul1_sw1={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 33} + }, + ttl_urukul1_sw2={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 34} + }, + ttl_urukul1_sw3={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 35} + }, + urukul1_cpld={ + "type": "local", + "module": "artiq.coredevice.urukul", + "class": "CPLD", + "arguments": { + "spi_device": "spi_urukul1", + "io_update_device": "ttl_urukul1_io_update", + "refclk": 125e6, + "clk_sel": 0 + } + } +) + +for i in range(4): + device_db["urukul1_ch" + str(i)] = { + "type": "local", + "module": "artiq.coredevice.ad9910", + "class": "AD9910", + "arguments": { + "pll_n": 32, + "chip_select": 4 + i, + "cpld_device": "urukul1_cpld", + "sw_device": "ttl_urukul1_sw" + str(i) + } + } + +device_db.update( + led0={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 36} + }, + led1={ + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 37} + } +) diff --git a/artiq/examples/kasli_ustc/repository/demo.py b/artiq/examples/kasli_ustc/repository/demo.py new file mode 100644 index 000000000..169856a08 --- /dev/null +++ b/artiq/examples/kasli_ustc/repository/demo.py @@ -0,0 +1,82 @@ +from artiq.experiment import * + + +class UrukulTest(EnvExperiment): + def build(self): + self.setattr_device("core") + self.setattr_device("urukul0_cpld") + self.setattr_device("urukul0_ch0") + self.setattr_device("urukul0_ch1") + self.setattr_device("urukul0_ch2") + self.setattr_device("urukul0_ch3") + self.setattr_device("urukul1_cpld") + self.setattr_device("urukul1_ch0") + self.setattr_device("urukul1_ch1") + self.setattr_device("urukul1_ch2") + self.setattr_device("urukul1_ch3") + self.setattr_device("led0") + self.ttl = self.get_device("ttl16") + + @kernel + def run(self): + self.core.reset() + self.ttl.output() + delay(1*us) + + self.urukul0_cpld.init() + self.urukul0_ch0.init() + self.urukul0_ch1.init() + self.urukul0_ch2.init() + self.urukul0_ch3.init() + self.urukul1_cpld.init() + self.urukul1_ch0.init() + self.urukul1_ch1.init() + self.urukul1_ch2.init() + self.urukul1_ch3.init() + + delay(1000*us) + self.urukul0_ch0.set(10*MHz) + self.urukul0_ch0.sw.on() + self.urukul0_ch0.set_att(10.) + + delay(1000*us) + self.urukul0_ch1.set(20*MHz, 0.5) + self.urukul0_ch1.sw.on() + self.urukul0_ch1.set_att(8.) + + delay(1000*us) + self.urukul0_ch2.set(30*MHz) + self.urukul0_ch2.sw.on() + self.urukul0_ch2.set_att(6.) + + delay(1000*us) + self.urukul0_ch3.set(40*MHz) + self.urukul0_ch3.sw.on() + self.urukul0_ch3.set_att(4.) + + delay(1000*us) + self.urukul1_ch0.set(15*MHz) + self.urukul1_ch0.sw.on() + self.urukul1_ch0.set_att(10.) + + delay(1000*us) + self.urukul1_ch1.set(25*MHz, 0.5) + self.urukul1_ch1.sw.on() + self.urukul1_ch1.set_att(8.) + + delay(1000*us) + self.urukul1_ch2.set(35*MHz) + self.urukul1_ch2.sw.on() + self.urukul1_ch2.set_att(6.) + + delay(1000*us) + self.urukul1_ch3.set(45*MHz) + self.urukul1_ch3.sw.on() + self.urukul1_ch3.set_att(4.) + + while True: + with parallel: + self.ttl.pulse(100*ms) + self.urukul0_ch0.sw.pulse(100*ms) + delay(100*ms) + self.led0.pulse(100*ms) diff --git a/artiq/frontend/artiq_flash.py b/artiq/frontend/artiq_flash.py index fb6610297..7058c287a 100755 --- a/artiq/frontend/artiq_flash.py +++ b/artiq/frontend/artiq_flash.py @@ -268,7 +268,8 @@ def main(): }, "kasli": { "programmer": partial(ProgrammerXC7, board="kasli", proxy="bscan_spi_xc7a100t.bit"), - "variants": ["opticlock", "suservo", "sysu", "mitll", "master", "satellite"], + "variants": ["opticlock", "suservo", "sysu", "mitll", "ustc", + "master", "satellite"], "gateware": ("spi0", 0x000000), "bootloader": ("spi0", 0x400000), "storage": ("spi0", 0x440000), diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index b3bce96fe..b1d0ea70e 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -630,7 +630,11 @@ class SYSU(_StandaloneBase): for i in range(40): eem_offset, port = divmod(i, 8) pads = platform.request("eem{}".format(2 + eem_offset), port) - phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) + if i < 4: + cls = ttl_serdes_7series.InOut_8X + else: + cls = ttl_serdes_7series.Output_8X + phy = cls(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) @@ -727,6 +731,63 @@ class MITLL(_StandaloneBase): self.add_rtio(rtio_channels) +class USTC(_StandaloneBase): + def __init__(self, hw_rev=None, **kwargs): + if hw_rev is None: + hw_rev = "v1.1" + _StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) + + self.config["SI5324_AS_SYNTHESIZER"] = None + self.config["RTIO_FREQUENCY"] = "125.0" + + platform = self.platform + # TODO: grabber on eem0->eemA + platform.add_extension(_urukul("eem2", "eem1")) + platform.add_extension(_urukul("eem4", "eem3")) + platform.add_extension(_dio("eem5")) + platform.add_extension(_dio("eem6")) + platform.add_extension(_dio("eem7")) + + # EEM5-7: TTL + rtio_channels = [] + for i in range(24): + eem_offset, port = divmod(i, 8) + pads = platform.request("eem{}".format(5 + eem_offset), port) + phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + # EEM2-4: Urukul + for eem in (2, 4): + phy = spi2.SPIMaster(self.platform.request("eem{}_spi_p".format(eem)), + self.platform.request("eem{}_spi_n".format(eem))) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) + + pads = platform.request("eem{}_dds_reset".format(eem)) + self.specials += DifferentialOutput(0, pads.p, pads.n) + + for signal in "io_update sw0 sw1 sw2 sw3".split(): + pads = platform.request("eem{}_{}".format(eem, signal)) + phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + for i in (1, 2): + sfp_ctl = platform.request("sfp_ctl", i) + phy = ttl_simple.Output(sfp_ctl.led) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + print(len(rtio_channels)) + + self.config["HAS_RTIO_LOG"] = None + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.LogChannel()) + + self.add_rtio(rtio_channels) + + class _RTIOClockMultiplier(Module): def __init__(self, rtio_clk_freq): self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) @@ -1037,7 +1098,8 @@ def main(): soc_kasli_args(parser) parser.set_defaults(output_dir="artiq_kasli") parser.add_argument("-V", "--variant", default="opticlock", - help="variant: opticlock/suservo/sysu/mitll/master/satellite " + help="variant: opticlock/suservo/sysu/mitll/ustc/" + "master/satellite " "(default: %(default)s)") args = parser.parse_args() @@ -1050,6 +1112,8 @@ def main(): cls = SYSU elif variant == "mitll": cls = MITLL + elif variant == "ustc": + cls = USTC elif variant == "master": cls = Master elif variant == "satellite":