mirror of https://github.com/m-labs/artiq.git
Merge branch 'master' of github.com:m-labs/artiq
This commit is contained in:
commit
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from artiq.language.core import kernel, portable, delay
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from artiq.language.units import ns
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from artiq.coredevice import spi
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_AD5360_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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_AD5360_CMD_DATA = 3 << 22
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_AD5360_CMD_OFFSET = 2 << 22
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_AD5360_CMD_GAIN = 1 << 22
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_AD5360_CMD_SPECIAL = 0 << 22
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@portable
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def _AD5360_WRITE_CHANNEL(c):
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return (c + 8) << 16
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_AD5360_SPECIAL_NOP = 0 << 16
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_AD5360_SPECIAL_CONTROL = 1 << 16
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_AD5360_SPECIAL_OFS0 = 2 << 16
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_AD5360_SPECIAL_OFS1 = 3 << 16
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_AD5360_SPECIAL_READ = 3 << 16
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@portable
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def _AD5360_READ_CHANNEL(ch):
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return (ch + 8) << 7
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_AD5360_READ_X1A = 0x000 << 7
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_AD5360_READ_X1B = 0x040 << 7
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_AD5360_READ_OFFSET = 0x080 << 7
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_AD5360_READ_GAIN = 0x0c0 << 7
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_AD5360_READ_CONTROL = 0x101 << 7
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_AD5360_READ_OFS0 = 0x102 << 7
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_AD5360_READ_OFS1 = 0x103 << 7
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class AD5360:
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"""
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Support for the Analog devices AD53[67][0123]
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multi-channel Digital to Analog Converters
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"""
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def __init__(self, dmgr, spi_bus, ldac=None, chip_select=0):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_bus)
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if ldac is not None:
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ldac = dmgr.get(ldac)
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self.ldac = ldac
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self.chip_select = chip_select
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@kernel
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def setup_bus(self, write_div=4, read_div=7):
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# write: 2*8ns >= 10ns = t_6 (clk falling to cs_n rising)
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# read: 4*8*ns >= 25ns = t_22 (clk falling to miso valid)
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self.bus.set_config_mu(_AD5360_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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@kernel
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def write_offsets(self, value=0x1fff):
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value &= 0x3fff
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS0 | value
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) << 8)
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_OFS1 | value
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) << 8)
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@kernel
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def write_channel(self, channel=0, value=0, op=_AD5360_CMD_DATA):
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channel &= 0x3f
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value &= 0xffff
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self.bus.write((op | _AD5360_WRITE_CHANNEL(channel) | value) << 8)
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@kernel
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def write_channels(self, values, first=0, op=_AD5360_CMD_DATA):
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for i in range(len(values)):
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self.write_channel(i + first, values[i], op)
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@kernel
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def read_channel_sync(self, channel=0, op=_AD5360_READ_X1A):
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channel &= 0x3f
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_READ | op |
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_AD5360_READ_CHANNEL(channel)) << 8)
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self.bus.set_xfer(self.chip_select, 0, 24)
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self.bus.write((_AD5360_CMD_SPECIAL | _AD5360_SPECIAL_NOP) << 8)
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self.bus.read_async()
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self.bus.set_xfer(self.chip_select, 24, 0)
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return self.bus.input_async() & 0xffff
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@kernel
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def load(self):
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self.ldac.off()
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delay(24*ns)
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self.ldac.on()
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@ -1,71 +0,0 @@
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from artiq.language.core import (kernel, portable, delay, delay_mu, int)
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from artiq.language.units import ns
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from artiq.coredevice import spi
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_AD53xx_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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_AD53xx_MODE_WRITE_X1 = 3 << 22
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_AD53xx_MODE_WRITE_C = 2 << 22
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_AD53xx_MODE_WRITE_M = 1 << 22
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_AD53xx_MODE_SPECIAL = 0 << 22
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_AD53xx_GROUP = portable(lambda g: ((g + 1) << 19))
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_AD53xx_GROUP_ALL = 0 << 19
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_AD53xx_GROUP_01234 = 6 << 19
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_AD53xx_GROUP_1234 = 7 << 19
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_AD53xx_CHANNEL_ALL = 0 << 16
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_AD53xx_CHANNEL = portable(lambda g: g << 16)
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_AD53xx_SPECIAL_NOP = 0 << 16
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_AD53xx_SPECIAL_CONTROL = 1 << 16
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_AD53xx_SPECIAL_OFS0 = 2 << 16
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_AD53xx_SPECIAL_OFS1 = 3 << 16
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_AD53xx_SPECIAL_AB_SELECT = portable(lambda i: (i + 6) << 16)
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_AD53xx_SPECIAL_AB_SELECT_ALL = 11 << 16
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_AD53xx_READ_X1A = portable(lambda ch: (0x00 | (ch + 8)) << 7)
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_AD53xx_READ_X1B = portable(lambda ch: (0x40 | (ch + 8)) << 7)
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_AD53xx_READ_C = portable(lambda ch: (0x80 | (ch + 8)) << 7)
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_AD53xx_READ_M = portable(lambda ch: (0xc0 | (ch + 8)) << 7)
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_AD53xx_READ_CONTROL = 0x101 << 7
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_AD53xx_READ_OFS0 = 0x102 << 7
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_AD53xx_READ_OFS1 = 0x103 << 7
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_AD53xx_READ_AB_SELECT = portable(lambda i: (0x100 + (i + 6)) << 7)
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class AD53xx:
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def __init__(self, dmgr, spi_bus, ldac=None,
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chip_select=0, write_div=4, read_div=6):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_bus)
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if ldac is not None:
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ldac = dmgr.get(ldac)
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self.ldac = ldac
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self.chip_select = chip_select
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self.write_div = write_div
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self.read_div = read_div
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@kernel
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def bus_setup(self):
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self.bus.set_config_mu(_AD53xx_SPI_CONFIG, self.write_div,
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self.read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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@kernel
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def _channel_address(self, channel=0):
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return int((channel + 8) << 16)
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@kernel
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def write_x1(self, channel=0, value=0):
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ch = self._channel_address(channel)
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self.bus.write(_AD53xx_MODE_WRITE_X1 | ch | value)
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delay_mu(int(self.bus.xfer_period_mu + self.bus.write_period_mu))
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@kernel
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def load(self):
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self.ldac.off()
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delay(20*ns)
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self.ldac.on()
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@ -198,11 +198,11 @@ class SPIMaster:
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the previous transfer's read data is available in the
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``data`` register.
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This method advances the timeline by the duration of the
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RTIO-to-Wishbone bus transaction (three RTIO clock cycles).
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This method advances the timeline by the duration of the SPI transfer.
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If a transfer is to be chained, the timeline needs to be rewound.
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"""
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rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
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delay_mu(3*self.ref_period_mu)
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delay_mu(self.xfer_period_mu + self.write_period_mu)
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@kernel
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def read_async(self):
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@ -238,7 +238,7 @@ class TTLClockGen:
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# in RTIO cycles
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self.previous_timestamp = int(0, width=64)
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self.acc_width = 24
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self.acc_width = int(24, width=64)
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@portable
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def frequency_to_ftw(self, frequency):
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@ -264,7 +264,7 @@ class NIST_CLOCK(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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for i in range(1): # spi1 and spi2 collide in pinout with ttl
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for i in range(3):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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@ -30,6 +30,11 @@ These drivers are for the core device and the peripherals closely integrated int
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.. automodule:: artiq.coredevice.spi
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:members:
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:mod:`artiq.coredevice.ad5360` module
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-------------------------------------
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.. automodule:: artiq.coredevice.ad5360
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:members:
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:mod:`artiq.coredevice.exceptions` module
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-----------------------------------------
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