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soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC

This commit is contained in:
Sebastien Bourdeauducq 2014-10-21 18:40:08 +08:00
parent 61a50ee53c
commit 346cca9e90
1 changed files with 1 additions and 1 deletions
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soc/targets/artiq.py
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@ -41,7 +41,7 @@ class _TestGen(Module):
class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 10
"rtio": 12
}
csr_map.update(BaseSoC.csr_map)