From 342d6d756e57811ef3f0e05d7ca14d2d4bebb6df Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Fri, 14 Oct 2016 00:59:53 +0200 Subject: [PATCH] phaser: bypass gtx phalign --- artiq/gateware/targets/kc705.py | 1 + 1 file changed, 1 insertion(+) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 759f3a229..449cdabe1 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -466,6 +466,7 @@ class AD9154JESD(Module, AutoCSR): phy = JESD204BPhyTX( qpll, platform.request("ad9154_jesd", i), fabric_freq) platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate) + self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO platform.add_false_path_constraints( self.cd_jesd.clk, phy.gtx.cd_tx.clk)