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phaser: cap phy data width to 64 temporarily

This commit is contained in:
Robert Jördens 2016-11-18 15:46:59 +01:00
parent 7664b226f2
commit 342b9e977e
1 changed files with 2 additions and 1 deletions
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artiq/gateware/rtio/phy/sawg.py
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@ -16,7 +16,8 @@ class Channel(_ChannelPHY):
_ChannelPHY.__init__(self, *args, **kwargs) _ChannelPHY.__init__(self, *args, **kwargs)
self.phys = [] self.phys = []
for i in self.i: for i in self.i:
rl = rtlink.Interface(rtlink.OInterface(len(i.payload))) rl = rtlink.Interface(rtlink.OInterface(
min(64, len(i.payload)))) # FIXME
self.comb += [ self.comb += [
i.stb.eq(rl.o.stb), i.stb.eq(rl.o.stb),
rl.o.busy.eq(~i.ack), rl.o.busy.eq(~i.ack),