M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

gateware/soc: use new SDRAM API call

This commit is contained in:
Sebastien Bourdeauducq 2015-12-16 14:59:35 +08:00
parent 35acc33ef6
commit 33860820b9
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/soc.py
View File

@ -20,7 +20,7 @@ class AMPSoC:
self.submodules.timer0 = timer.Timer(width=64) self.submodules.timer0 = timer.Timer(width=64)
self.submodules.kernel_cpu = amp.KernelCPU(self.platform) self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
self.add_wb_sdram_if(self.kernel_cpu.wb_sdram) self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
self.submodules.mailbox = amp.Mailbox() self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),