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fir: check widths

This commit is contained in:
Robert Jördens 2017-06-12 20:07:23 +02:00
parent 39a1dcbb3d
commit 332bcc7f3b
1 changed files with 9 additions and 2 deletions
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11
artiq/gateware/dsp/fir.py
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@ -78,13 +78,20 @@ class ParallelFIR(Module):
c_shift = bits_for(floor((1 << w.B - 2) / c_max)) c_shift = bits_for(floor((1 << w.B - 2) / c_max))
self.coefficients = cs = [int(round(c*(1 << c_shift))) self.coefficients = cs = [int(round(c*(1 << c_shift)))
for c in coefficients] for c in coefficients]
assert max(bits_for(c) for c in cs) <= w.B
### ###
# Delay line: increasing delay # Delay line: increasing delay
x = [Signal((w.A, True)) for _ in range(n + p - 1)] x = [Signal((w.A, True)) for _ in range(n + p - 1)]
x_shift = w.A - width - bits_for( x_shift = w.A - width
max(cs.count(c) for c in cs if c) - 1) # reduce by pre-adder gain
x_shift -= bits_for(max(cs.count(c) for c in cs if c) - 1)
# TODO: reduce by P width limit?
assert x_shift + width <= w.A
assert sum(abs(c)*(1 << w.A - 1) for c in cs) <= (1 << w.P - 1) - 1
for xi, xj in zip(x, self.i[::-1]): for xi, xj in zip(x, self.i[::-1]):
self.sync += xi.eq(xj << x_shift) self.sync += xi.eq(xj << x_shift)
for xi, xj in zip(x[len(self.i):], x): for xi, xj in zip(x[len(self.i):], x):