From 3242e9ec6c254c463c2a418ae409bea46eea6774 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 13 Jan 2020 22:31:57 +0800 Subject: [PATCH] wrpll: loop test --- artiq/firmware/libboard_artiq/wrpll.rs | 39 +++++++++++++++++++++++++- artiq/gateware/drtio/wrpll/core.py | 20 ++++++++----- 2 files changed, 51 insertions(+), 8 deletions(-) diff --git a/artiq/firmware/libboard_artiq/wrpll.rs b/artiq/firmware/libboard_artiq/wrpll.rs index c1343df20..5df8eef1e 100644 --- a/artiq/firmware/libboard_artiq/wrpll.rs +++ b/artiq/firmware/libboard_artiq/wrpll.rs @@ -175,7 +175,7 @@ mod si549 { use board_misoc::clock; use super::i2c; - const ADDRESS: u8 = 0x55; + pub const ADDRESS: u8 = 0x55; pub fn write(dcxo: i2c::Dcxo, reg: u8, val: u8) -> Result<(), &'static str> { i2c::start(dcxo); @@ -270,6 +270,13 @@ mod si549 { clock::spin_us(100); Ok(()) } + + pub fn get_adpll(dcxo: i2c::Dcxo) -> Result { + let b1 = read(dcxo, 231)? as i32; + let b2 = read(dcxo, 232)? as i32; + let b3 = read(dcxo, 233)? as i8 as i32; + Ok(b3 << 16 | b2 << 8 | b1) + } } fn get_frequencies() -> (u32, u32, u32) { @@ -315,6 +322,11 @@ pub fn init() { unsafe { csr::wrpll::helper_reset_write(1); } + unsafe { + csr::wrpll::helper_dcxo_i2c_address_write(si549::ADDRESS); + csr::wrpll::main_dcxo_i2c_address_write(si549::ADDRESS); + } + #[cfg(rtio_frequency = "125.0")] let (h_hsdiv, h_lsdiv, h_fbdiv) = (0x05c, 0, 0x04b5badb98a); #[cfg(rtio_frequency = "125.0")] @@ -403,16 +415,41 @@ fn select_recovered_clock_int(rc: bool) -> Result<(), &'static str> { let (helper_adpll, main_adpll) = trim_dcxos(f_helper, f_main, f_cdr)?; si549::set_adpll(i2c::Dcxo::Helper, helper_adpll).expect("ADPLL write failed"); si549::set_adpll(i2c::Dcxo::Main, main_adpll).expect("ADPLL write failed"); + unsafe { csr::wrpll::adpll_offset_helper_write(helper_adpll as u32); csr::wrpll::adpll_offset_main_write(main_adpll as u32); + csr::wrpll::helper_dcxo_gpio_enable_write(0); + csr::wrpll::main_dcxo_gpio_enable_write(0); + csr::wrpll::helper_dcxo_errors_write(0xff); + csr::wrpll::main_dcxo_errors_write(0xff); + csr::wrpll::filter_reset_write(0); } + clock::spin_us(100_000); + let mut tags = [0; 10]; for i in 0..tags.len() { tags[i] = get_ddmtd_helper_tag(); } info!("DDMTD helper tags: {:?}", tags); + + unsafe { + csr::wrpll::filter_reset_write(1); + } + clock::spin_us(50_000); + unsafe { + csr::wrpll::helper_dcxo_gpio_enable_write(1); + csr::wrpll::main_dcxo_gpio_enable_write(1); + } + unsafe { + info!("error {} {}", + csr::wrpll::helper_dcxo_errors_read(), + csr::wrpll::main_dcxo_errors_read()); + } + info!("new ADPLL: {} {}", + si549::get_adpll(i2c::Dcxo::Helper)?, + si549::get_adpll(i2c::Dcxo::Main)?); } else { si549::set_adpll(i2c::Dcxo::Helper, 0).expect("ADPLL write failed"); si549::set_adpll(i2c::Dcxo::Main, 0).expect("ADPLL write failed"); diff --git a/artiq/gateware/drtio/wrpll/core.py b/artiq/gateware/drtio/wrpll/core.py index ad2dd4e3c..a8d374ca8 100644 --- a/artiq/gateware/drtio/wrpll/core.py +++ b/artiq/gateware/drtio/wrpll/core.py @@ -51,15 +51,21 @@ class FrequencyCounter(Module, AutoCSR): class WRPLL(Module, AutoCSR): def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c, ddmtd_inputs, N=15): self.helper_reset = CSRStorage(reset=1) + self.filter_reset = CSRStorage(reset=1) self.adpll_offset_helper = CSRStorage(24) self.adpll_offset_main = CSRStorage(24) self.clock_domains.cd_helper = ClockDomain() + self.clock_domains.cd_filter = ClockDomain() self.helper_reset.storage.attr.add("no_retiming") + self.filter_reset.storage.attr.add("no_retiming") + self.specials += Instance("IBUFGDS", + i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n, + o_O=self.cd_helper.clk) + self.comb += self.cd_filter.clk.eq(self.cd_helper.clk) self.specials += [ - Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n, - o_O=self.cd_helper.clk), - AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage) + AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage), + AsyncResetSynchronizer(self.cd_filter, self.filter_reset.storage) ] self.submodules.helper_dcxo = Si549(helper_dxco_i2c) @@ -73,10 +79,10 @@ class WRPLL(Module, AutoCSR): self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk) self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo) - helper_cd = ClockDomainsRenamer("helper") - self.submodules.collector = helper_cd(Collector(N)) - self.submodules.filter_helper = helper_cd(thls.make(filters.helper, data_width=48)) - self.submodules.filter_main = helper_cd(thls.make(filters.main, data_width=48)) + filter_cd = ClockDomainsRenamer("filter") + self.submodules.collector = filter_cd(Collector(N)) + self.submodules.filter_helper = filter_cd(thls.make(filters.helper, data_width=48)) + self.submodules.filter_main = filter_cd(thls.make(filters.main, data_width=48)) self.comb += [ self.collector.tag_helper.eq(self.ddmtd_helper.h_tag),