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update NAC3, restore original delays

This commit is contained in:
Sebastien Bourdeauducq 2021-12-06 12:21:52 +08:00
parent 61d3e22ea8
commit 31ac6881df
4 changed files with 7 additions and 12 deletions
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4
artiq/coredevice/ad53xx.py
View File

@ -196,7 +196,7 @@ class AD53xx:
if (ctrl & 0b10000) != 0: if (ctrl & 0b10000) != 0:
# NAC3TODO raise ValueError("DAC over temperature") # NAC3TODO raise ValueError("DAC over temperature")
pass pass
self.core.delay(125.*us) # NAC3TODO try to restore original 25us after kernel invariants self.core.delay(25.*us)
self.bus.write( # enable power and overtemperature shutdown self.bus.write( # enable power and overtemperature shutdown
(AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_CONTROL | 0b0010) << 8) (AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_CONTROL | 0b0010) << 8)
if not blind: if not blind:
@ -204,7 +204,7 @@ class AD53xx:
if (ctrl & 0b10111) != 0b00010: if (ctrl & 0b10111) != 0b00010:
# NAC3TODO raise ValueError("DAC CONTROL readback mismatch") # NAC3TODO raise ValueError("DAC CONTROL readback mismatch")
pass pass
self.core.delay(115.*us) # NAC3TODO try to restore original 15us after kernel invariants self.core.delay(15.*us)
@kernel @kernel
def read_reg(self, channel: int32 = 0, op: int32 = AD53XX_READ_X1A) -> int32: def read_reg(self, channel: int32 = 0, op: int32 = AD53XX_READ_X1A) -> int32:

2
artiq/coredevice/ad9912.py
View File

@ -108,7 +108,7 @@ class AD9912:
if (prodid != 0x1982) and (prodid != 0x1902): if (prodid != 0x1982) and (prodid != 0x1902):
# NAC3TODO raise ValueError("Urukul AD9912 product id mismatch") # NAC3TODO raise ValueError("Urukul AD9912 product id mismatch")
pass pass
self.core.delay(300. * us) # NAC3TODO try to restore 50us after kernel invariants are implemented self.core.delay(50. * us)
# HSTL power down, CMOS power down # HSTL power down, CMOS power down
self.write(AD9912_PWRCNTRL1, 0x80, 1) self.write(AD9912_PWRCNTRL1, 0x80, 1)
self.cpld.io_update.pulse(2. * us) self.cpld.io_update.pulse(2. * us)

5
artiq/examples/nac3devices/nac3devices.py
View File

@ -27,23 +27,18 @@ class NAC3Devices(EnvExperiment):
@kernel @kernel
def run(self): def run(self):
self.core.reset() self.core.reset()
self.core.delay(1.*ms)
self.zotino0.init() self.zotino0.init()
self.zotino0.set_leds(0x15) self.zotino0.set_leds(0x15)
self.core.delay(1.*ms)
self.zotino0.set_dac([1.2, -5.3, 3.4, 4.5], [0, 1, 2, 3]) self.zotino0.set_dac([1.2, -5.3, 3.4, 4.5], [0, 1, 2, 3])
self.core.break_realtime() self.core.break_realtime()
self.core.delay(1.*ms)
self.mirny0_cpld.init() self.mirny0_cpld.init()
self.mirny0_ch0.init() self.mirny0_ch0.init()
self.mirny0_ch0.set_att_mu(160) self.mirny0_ch0.set_att_mu(160)
self.mirny0_ch0.sw.on() self.mirny0_ch0.sw.on()
self.core.break_realtime()
self.mirny0_ch0.set_frequency(2500.*MHz) self.mirny0_ch0.set_frequency(2500.*MHz)
self.core.break_realtime() self.core.break_realtime()
self.core.delay(1.*ms)
self.urukul0_cpld.init() self.urukul0_cpld.init()
self.urukul0_ch0.init() self.urukul0_ch0.init()
self.urukul0_ch0.sw.on() self.urukul0_ch0.sw.on()

8
flake.lock
View File

@ -80,11 +80,11 @@
"nixpkgs": "nixpkgs" "nixpkgs": "nixpkgs"
}, },
"locked": { "locked": {
"lastModified": 1638686158, "lastModified": 1638707403,
"narHash": "sha256-x3DSzTZEhpTt2PKIx/HZ+5PuD56ytc6HOZtra/yyInI=", "narHash": "sha256-NcGX9uS5/Gb1geUo4NEZsX5b+Eq9uWkT04iwUVQnHBg=",
"ref": "master", "ref": "master",
"rev": "d2919b9620c88756b73aa0cb13f9f014703b67c4", "rev": "6d00d4dabb54f6944a9c97981a1d3416093a3df9",
"revCount": 488, "revCount": 490,
"type": "git", "type": "git",
"url": "https://git.m-labs.hk/M-Labs/nac3.git" "url": "https://git.m-labs.hk/M-Labs/nac3.git"
}, },