mirror of https://github.com/m-labs/artiq
Merge branch 'master' into nac3
commit
313449f2bd
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@ -111,7 +111,7 @@ class Config:
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@nac3
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class Volt:
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class DCBias:
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"""Shuttler Core cubic DC-bias spline.
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A Shuttler channel can generate a waveform `w(t)` that is the sum of a
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@ -145,7 +145,7 @@ class Volt:
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def set_waveform(self, a0: int32, a1: int32, a2: int64, a3: int64):
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"""Set the DC-bias spline waveform.
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Given `a(t)` as defined in :class:`Volt`, the coefficients should be
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Given `a(t)` as defined in :class:`DCBias`, the coefficients should be
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configured by the following formulae.
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.. math::
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@ -189,7 +189,7 @@ class Volt:
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@nac3
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class Dds:
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class DDS:
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"""Shuttler Core DDS spline.
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A Shuttler channel can generate a waveform `w(t)` that is the sum of a
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@ -228,7 +228,7 @@ class Dds:
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c0: int32, c1: int32, c2: int32):
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"""Set the DDS spline waveform.
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Given `b(t)` and `c(t)` as defined in :class:`Dds`, the coefficients
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Given `b(t)` and `c(t)` as defined in :class:`DDS`, the coefficients
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should be configured by the following formulae.
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.. math::
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@ -308,7 +308,7 @@ class Trigger:
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Each bit corresponds to a Shuttler waveform generator core. Setting
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`trig_out` bits commits the pending coefficient update (from
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`set_waveform` in :class:`Volt` and :class:`Dds`) to the Shuttler Core
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`set_waveform` in :class:`DCBias` and :class:`DDS`) to the Shuttler Core
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synchronously.
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:param trig_out: Coefficient update trigger bits. The MSB corresponds
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@ -580,7 +580,7 @@ class ADC:
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self.core.delay(2500.*us)
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@kernel
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def calibrate(self, volts: list[Volt], trigger: Trigger, config: Config, samples: Option[list[float]] = none):
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def calibrate(self, volts: list[DCBias], trigger: Trigger, config: Config, samples: Option[list[float]] = none):
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"""Calibrate the Shuttler waveform generator using the ADC on the AFE.
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It finds the average slope rate and average offset by samples, and
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@ -599,7 +599,7 @@ class ADC:
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:meth:`Config.set_offset`
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:param volts: A list of all 16 cubic DC-bias spline.
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(See :class:`Volt`)
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(See :class:`DCBias`)
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:param trigger: The Shuttler spline coefficient update trigger.
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:param config: The Shuttler Core configuration registers.
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:param samples: A list of sample voltages for calibration. There must
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@ -1,12 +1,12 @@
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{
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"target": "kasli",
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"variant": "master",
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"variant": "shuttlerdemo",
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"hw_rev": "v2.0",
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"base": "master",
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"drtio_role": "master",
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"peripherals": [
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{
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"type": "shuttler",
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"ports": [0]
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"ports": [0]
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},
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{
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"type": "dio",
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@ -7,8 +7,8 @@ from artiq.coredevice.shuttler import (
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shuttler_volt_to_mu,
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Config as ShuttlerConfig,
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Trigger as ShuttlerTrigger,
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Volt as ShuttlerDCBias,
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Dds as ShuttlerDDS,
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DCBias as ShuttlerDCBias,
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DDS as ShuttlerDDS,
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Relay as ShuttlerRelay,
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ADC as ShuttlerADC)
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@ -70,7 +70,7 @@ class Shuttler(EnvExperiment):
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shuttler0_leds: KernelInvariant[list[TTLOut]]
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shuttler0_config: KernelInvariant[ShuttlerConfig]
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shuttler0_trigger: KernelInvariant[ShuttlerTrigger]
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shuttler0_volt: KernelInvariant[list[ShuttlerDCBias]]
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shuttler0_dcbias: KernelInvariant[list[ShuttlerDCBias]]
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shuttler0_dds: KernelInvariant[list[ShuttlerDDS]]
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shuttler0_relay: KernelInvariant[ShuttlerRelay]
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shuttler0_adc: KernelInvariant[ShuttlerADC]
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@ -81,7 +81,7 @@ class Shuttler(EnvExperiment):
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self.shuttler0_leds = [ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ]
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self.setattr_device("shuttler0_config")
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self.setattr_device("shuttler0_trigger")
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self.shuttler0_volt = [ self.get_device("shuttler0_volt{}".format(i)) for i in range(16) ]
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self.shuttler0_dcbias = [ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ]
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self.shuttler0_dds = [ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ]
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self.setattr_device("shuttler0_relay")
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self.setattr_device("shuttler0_adc")
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@ -114,7 +114,7 @@ class Shuttler(EnvExperiment):
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@kernel
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def shuttler_channel_reset(self, ch: int32):
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self.shuttler0_volt[ch].set_waveform(
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self.shuttler0_dcbias[ch].set_waveform(
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a0=0,
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a1=0,
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a2=int64(0),
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@ -238,7 +238,7 @@ class Shuttler(EnvExperiment):
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self.core.delay(500.*us)
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## Step 5 ##
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self.shuttler0_volt[0].set_waveform(
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self.shuttler0_dcbias[0].set_waveform(
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a0=shuttler_volt_amp_mu(-5.0),
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a1=int32(shuttler_volt_damp_mu(0.01)),
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a2=int64(0),
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@ -253,7 +253,7 @@ class Shuttler(EnvExperiment):
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c1=shuttler_freq_mu(end_f_MHz),
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c2=0,
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)
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self.shuttler0_volt[1].set_waveform(
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self.shuttler0_dcbias[1].set_waveform(
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a0=shuttler_volt_amp_mu(-5.0),
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a1=int32(shuttler_volt_damp_mu(0.01)),
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a2=int64(0),
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@ -272,7 +272,7 @@ class Shuttler(EnvExperiment):
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self.core.delay(1000.*us)
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## Step 6 ##
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self.shuttler0_volt[0].set_waveform(
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self.shuttler0_dcbias[0].set_waveform(
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a0=shuttler_volt_amp_mu(-2.5),
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a1=int32(shuttler_volt_damp_mu(0.01)),
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a2=int64(0),
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@ -292,7 +292,7 @@ class Shuttler(EnvExperiment):
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self.core.delay(500.*us)
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## Step 7 ##
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self.shuttler0_volt[0].set_waveform(
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self.shuttler0_dcbias[0].set_waveform(
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a0=shuttler_volt_amp_mu(2.5),
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a1=int32(shuttler_volt_damp_mu(-0.01)),
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a2=int64(0),
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@ -339,4 +339,4 @@ class Shuttler(EnvExperiment):
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# The actual output voltage is limited by the hardware, the calculated calibration gain and offset.
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# For example, if the system has a calibration gain of 1.06, then the max output voltage = 10 / 1.06 = 9.43V.
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# Setting a value larger than 9.43V will result in overflow.
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self.shuttler0_adc.calibrate(self.shuttler0_volt, self.shuttler0_trigger, self.shuttler0_config)
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self.shuttler0_adc.calibrate(self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config)
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@ -14,7 +14,7 @@ from artiq.coredevice.edge_counter import EdgeCounter
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from artiq.coredevice.grabber import Grabber
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from artiq.coredevice.fastino import Fastino
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from artiq.coredevice.phaser import Phaser
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from artiq.coredevice.shuttler import Volt as ShuttlerDCBias, Dds as ShuttlerDDS
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from artiq.coredevice.shuttler import DCBias as ShuttlerDCBias, DDS as ShuttlerDDS
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@nac3
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@ -35,7 +35,7 @@ class NAC3Devices(EnvExperiment):
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grabber0: KernelInvariant[Grabber]
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fastino0: KernelInvariant[Fastino]
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phaser0: KernelInvariant[Phaser]
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shuttler0_volt0: KernelInvariant[ShuttlerDCBias]
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shuttler0_dcbias0: KernelInvariant[ShuttlerDCBias]
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shuttler0_dds0: KernelInvariant[ShuttlerDDS]
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def build(self):
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@ -55,7 +55,7 @@ class NAC3Devices(EnvExperiment):
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self.setattr_device("grabber0")
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self.setattr_device("fastino0")
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self.setattr_device("phaser0")
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self.setattr_device("shuttler0_volt0")
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self.setattr_device("shuttler0_dcbias0")
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self.setattr_device("shuttler0_dds0")
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@kernel
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@ -624,10 +624,10 @@ class PeripheralManager:
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channel=rtio_offset + next(channel))
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for i in range(16):
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self.gen("""
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device_db["{name}_volt{ch}"] = {{
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device_db["{name}_dcbias{ch}"] = {{
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"type": "local",
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"module": "artiq.coredevice.shuttler",
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"class": "Volt",
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"class": "DCBias",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}""",
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name=shuttler_name,
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@ -637,7 +637,7 @@ class PeripheralManager:
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device_db["{name}_dds{ch}"] = {{
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"type": "local",
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"module": "artiq.coredevice.shuttler",
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"class": "Dds",
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"class": "DDS",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}""",
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name=shuttler_name,
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@ -729,16 +729,26 @@ def process(output, primary_description, satellites):
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peripherals, satellite_drtio_peripherals = split_drtio_eem(description["peripherals"])
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drtio_peripherals.extend(satellite_drtio_peripherals)
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print("# DEST#{} peripherals".format(destination), file=output)
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print("device_db[\"satellite_cpu_targets\"][{}] = \"{}\"".format(destination, get_cpu_target(description)), file=output)
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print(textwrap.dedent("""
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# DEST#{dest} peripherals
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device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
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dest=destination,
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target=get_cpu_target(description)),
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file=output)
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rtio_offset = destination << 16
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for peripheral in peripherals:
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n_channels = pm.process(rtio_offset, peripheral)
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rtio_offset += n_channels
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for peripheral in drtio_peripherals:
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print("# DEST#{} peripherals".format(peripheral["drtio_destination"]), file=output)
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print("device_db[\"satellite_cpu_targets\"][{}] = \"{}\"".format(peripheral["drtio_destination"], get_cpu_target(peripheral)), file=output)
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print(textwrap.dedent("""
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# DEST#{dest} peripherals
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device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
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dest=peripheral["drtio_destination"],
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target=get_cpu_target(peripheral)),
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file=output)
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processor = getattr(pm, "process_"+str(peripheral["type"]))
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processor(peripheral)
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