From 30d1acee9f7e8c642df3d9c1ba5b67e501b37b39 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Sun, 18 Oct 2020 22:27:05 +0200 Subject: [PATCH] fastlink: fix fastino style link --- artiq/gateware/rtio/phy/fastlink.py | 9 ++++----- artiq/gateware/test/rtio/test_fastlink.py | 12 +++--------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/artiq/gateware/rtio/phy/fastlink.py b/artiq/gateware/rtio/phy/fastlink.py index 796b01642..1a9317f77 100644 --- a/artiq/gateware/rtio/phy/fastlink.py +++ b/artiq/gateware/rtio/phy/fastlink.py @@ -74,9 +74,8 @@ class SerDes(Module): # big shift register for mosi and sr = [Signal(t_frame, reset_less=True) for i in range(n_mosi)] assert len(Cat(sr)) == len(words) - crc_insert = ([d[1] for d in self.data[:-1]] + - [d[0] for d in self.data[:-1]]) - crc_insert = Cat(crc_insert[-n_crc:]) + crc_insert = Cat(([d[0] for d in self.data[1:-1]] + + [d[1] for d in self.data[1:-1]])[:n_crc]) miso_sr = Signal(t_frame, reset_less=True) miso_sr_next = Signal.like(miso_sr) self.comb += [ @@ -106,8 +105,8 @@ class SerDes(Module): # transpose, load [sri.eq(Cat(words[i::n_mosi])) for i, sri in enumerate(sr)], # inject crc for the last cycle - crc_insert.eq(self.crca.next if n_crc // n_mosi == 1 - else self.crcb.next), + crc_insert.eq(self.crca.next if n_crc // n_mosi <= 1 + else self.crca.last), ), ] diff --git a/artiq/gateware/test/rtio/test_fastlink.py b/artiq/gateware/test/rtio/test_fastlink.py index 3733e8205..df8840951 100644 --- a/artiq/gateware/test/rtio/test_fastlink.py +++ b/artiq/gateware/test/rtio/test_fastlink.py @@ -36,8 +36,7 @@ class TestPhaser(unittest.TestCase): frame = [] self.dut.comb += self.dut.payload.eq((1 << len(self.dut.payload)) - 1) run_simulation(self.dut, self.record_frame(frame), - clocks={n: 2 for n in ["sys", "rio", "rio_phy"]}, - vcd_name="fastlink.vcd") + clocks={n: 2 for n in ["sys", "rio", "rio_phy"]}) self.assertEqual(len(frame), 8*10//2) self.assertEqual([d[0] for d in frame], [0, 0, 3, 3] * 10) self.assertEqual([d[1] & 1 for d in frame[4*4 - 1:10*4 - 1:4]], @@ -79,12 +78,7 @@ class TestFastino(unittest.TestCase): frame = [] self.dut.comb += self.dut.payload.eq((1 << len(self.dut.payload)) - 1) run_simulation(self.dut, self.record_frame(frame), - clocks={n: 2 for n in ["sys", "rio", "rio_phy"]}, - vcd_name="fastlink.vcd") + clocks={n: 2 for n in ["sys", "rio", "rio_phy"]}) self.assertEqual(len(frame), 7*14//2) self.assertEqual([d[0] for d in frame], [3, 0, 1, 3, 2, 0, 3] * 7) - self.assertEqual(ref, frame) - print(frame) - - -ref = [[3, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [1, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [2, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [1, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [2, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [1, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [2, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [3, 2, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [1, 3, 3, 3, 3, 3, 3, 0], [3, 1, 3, 3, 3, 3, 3, 0], [2, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [3, 2, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [1, 3, 3, 3, 3, 3, 3, 0], [3, 1, 3, 3, 3, 3, 3, 0], [2, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [3, 2, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [1, 3, 3, 3, 3, 3, 3, 0], [3, 1, 3, 3, 3, 3, 3, 0], [2, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [3, 2, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [1, 3, 3, 3, 3, 3, 3, 0], [3, 3, 3, 3, 3, 3, 3, 0], [2, 3, 3, 3, 3, 3, 3, 0], [0, 3, 3, 3, 3, 3, 3, 0], [3, 3, 1, 1, 1, 2, 1, 0]] + self.assertEqual(frame[-1], [3, 3, 1, 1, 1, 2, 1, 0]) # crc12