unflip logic..

2022-06-23 10:20:38 +00:00 · 2022-06-23 10:20:38 +00:00 · 2e834cf406
parent 3f8a221c76
commit 2e834cf406
1 changed files with 1 additions and 1 deletions
--- a/artiq/coredevice/phaser.py
+++ b/artiq/coredevice/phaser.py
@ -1094,7 +1094,7 @@ class PhaserChannel:
            raise ValueError("invalid profile index")
        addr = PHASER_ADDR_SERVO_CFG0 + self.index
        # enforce hold if the servo is bypassed
-        data = (profile << 2) | (((hold | bypass) & 1) << 1) | (bypass & 1)
+        data = (profile << 2) | (((hold | bypass) & 1) << 1) | (~bypass & 1)
        self.phaser.write8(addr, data)

    @kernel