Rust: add some conditional compilation back to rtio_crg.

artiq/runtime.rs/src/rtio_crg.rs

@@ -1,8 +1,42 @@
+use config;
+
+#[cfg(has_rtio_crg)]
+mod imp {
     use board::csr;
-use {clock, config};
+    use clock;
 
     pub fn init() {
         unsafe { csr::rtio_crg::pll_reset_write(0) }
+    }
+
+    pub fn check() -> bool {
+        unsafe { csr::rtio_crg::pll_locked_read() != 0 }
+    }
+
+    pub fn switch_clock(clk: u8) -> bool {
+        unsafe {
+            let cur_clk = csr::rtio_crg::clock_sel_read();
+            if clk != cur_clk {
+                csr::rtio_crg::pll_reset_write(1);
+                csr::rtio_crg::clock_sel_write(clk);
+                csr::rtio_crg::pll_reset_write(0);
+            }
+        }
+
+        clock::spin_us(150);
+        return check()
+    }
+}
+
+#[cfg(not(has_rtio_crg))]
+mod imp {
+    pub fn init() {}
+    pub fn check() -> bool { true }
+    pub fn switch_clock(clk: u8) -> bool { true }
+}
+
+pub fn init() {
+    imp::init();
 
     let mut opt = [b'i'];
     let clk;
@@ -28,20 +62,4 @@ pub fn init() {
     }
 }
 
-pub fn check() -> bool {
-    unsafe { csr::rtio_crg::pll_locked_read() != 0 }
-}
-
-pub fn switch_clock(clk: u8) -> bool {
-    unsafe {
-        let cur_clk = csr::rtio_crg::clock_sel_read();
-        if clk != cur_clk {
-            csr::rtio_crg::pll_reset_write(1);
-            csr::rtio_crg::clock_sel_write(clk);
-            csr::rtio_crg::pll_reset_write(0);
-        }
-    }
-
-    clock::spin_us(150);
-    return check()
-}
+pub use self::imp::{check, switch_clock};