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https://github.com/m-labs/artiq.git
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Remove added whitespace
This commit is contained in:
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18dab3aace
commit
2d658a83fb
@ -16,7 +16,7 @@ __all__ = [
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"PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE", "PHASE_MODE_TRACKING",
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"RAM_DEST_FTW", "RAM_DEST_POW", "RAM_DEST_ASF", "RAM_DEST_POWASF",
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"RAM_MODE_DIRECTSWITCH", "RAM_MODE_RAMPUP", "RAM_MODE_BIDIR_RAMP",
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"RAM_MODE_CONT_BIDIR_RAMP", "RAM_MODE_CONT_RAMPUP",
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"RAM_MODE_CONT_BIDIR_RAMP", "RAM_MODE_CONT_RAMPUP",
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]
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_PHASE_MODE_DEFAULT = -1
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@ -162,7 +162,7 @@ class AD9910:
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assert 12 <= pll_n <= 127
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assert 0 <= pll_vco <= 5
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vco_min, vco_max = [(370, 510), (420, 590), (500, 700),
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(600, 880), (700, 950), (820, 1150)][pll_vco]
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(600, 880), (700, 950), (820, 1150)][pll_vco]
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assert vco_min <= sysclk / 1e6 <= vco_max
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assert 0 <= pll_cp <= 7
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else:
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@ -178,7 +178,7 @@ class AD9910:
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if isinstance(sync_delay_seed, str) or isinstance(io_update_delay, str):
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if sync_delay_seed != io_update_delay:
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raise ValueError("When using EEPROM, sync_delay_seed must be "
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"equal to io_update_delay")
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"equal to io_update_delay")
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self.sync_data = SyncDataEeprom(dmgr, self.core, sync_delay_seed)
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else:
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self.sync_data = SyncDataUser(self.core, sync_delay_seed,
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@ -238,7 +238,7 @@ class AD9910:
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 24,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr << 24) | ((data & 0xFFFF) << 8))
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self.bus.write((addr << 24) | ((data & 0xFFFF) << 8))
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@kernel
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def write32(self, addr: TInt32, data: TInt32):
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@ -248,10 +248,10 @@ class AD9910:
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:param data: Data to be written
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(addr << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(data)
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@kernel
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@ -261,11 +261,11 @@ class AD9910:
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:param addr: Register address
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | 0x80) << 24)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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16, urukul.SPIT_DDS_RD, self.chip_select)
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16, urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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return self.bus.read()
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@ -276,7 +276,7 @@ class AD9910:
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:param addr: Register address
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | 0x80) << 24)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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@ -293,15 +293,15 @@ class AD9910:
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"""
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self.bus.set_config_mu(
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urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | 0x80) << 24)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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hi = self.bus.read()
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lo = self.bus.read()
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@ -316,13 +316,13 @@ class AD9910:
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:param data_low: Low (LSB) 32 data bits
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(addr << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(data_high)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(data_low)
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@kernel
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@ -336,15 +336,15 @@ class AD9910:
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:param data: Data to be written to RAM.
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
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self.chip_select)
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self.bus.write(_AD9910_REG_RAM << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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for i in range(len(data) - 1):
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self.bus.write(data[i])
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.write(data[len(data) - 1])
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@kernel
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@ -359,12 +359,12 @@ class AD9910:
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:param data: List to be filled with data read from RAM.
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
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self.chip_select)
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self.chip_select)
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self.bus.write((_AD9910_REG_RAM | 0x80) << 24)
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n = len(data) - 1
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if n > 0:
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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urukul.SPIT_DDS_RD, self.chip_select)
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preload = min(n, 8)
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for i in range(n):
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self.bus.write(0)
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@ -372,7 +372,7 @@ class AD9910:
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data[i - preload] = self.bus.read()
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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for i in range(preload + 1):
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data[(n - preload) + i] = self.bus.read()
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@ -389,7 +389,7 @@ class AD9910:
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ram_enable: TInt32 = 0,
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manual_osk_external: TInt32 = 0,
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osk_enable: TInt32 = 0,
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select_auto_osk: TInt32 = 0):
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select_auto_osk: TInt32 = 0):
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"""Set CFR1. See the AD9910 datasheet for parameter meanings and sizes.
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This method does not pulse ``IO_UPDATE.``
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@ -420,7 +420,7 @@ class AD9910:
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(osk_enable << 9) |
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(select_auto_osk << 8) |
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(power_down << 4) |
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2) # SDIO input only, MSB first
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2) # SDIO input only, MSB first
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@kernel
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def set_cfr2(self,
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@ -431,7 +431,7 @@ class AD9910:
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drg_nodwell_low: TInt32 = 0,
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effective_ftw: TInt32 = 1,
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sync_validation_disable: TInt32 = 0,
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matched_latency_enable: TInt32 = 0):
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matched_latency_enable: TInt32 = 0):
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"""Set CFR2. See the AD9910 datasheet for parameter meanings and sizes.
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This method does not pulse ``IO_UPDATE``.
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@ -458,7 +458,7 @@ class AD9910:
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(drg_nodwell_low << 17) |
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(effective_ftw << 16) |
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(matched_latency_enable << 7) |
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(sync_validation_disable << 5))
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(sync_validation_disable << 5))
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@kernel
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def init(self, blind: TBool = False):
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@ -496,7 +496,7 @@ class AD9910:
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self.cpld.io_update.pulse(1 * us)
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cfr3 = (0x0807c000 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_en << 8) |
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(self.pll_n << 1))
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(self.pll_n << 1))
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self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
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self.cpld.io_update.pulse(1 * us)
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if self.pll_en:
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@ -533,7 +533,7 @@ class AD9910:
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phase_mode: TInt32 = _PHASE_MODE_DEFAULT,
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ref_time_mu: TInt64 = int64(-1),
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profile: TInt32 = DEFAULT_PROFILE,
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ram_destination: TInt32 = -1) -> TInt32:
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ram_destination: TInt32 = -1) -> TInt32:
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"""Set DDS data in machine units.
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This uses machine units (FTW, POW, ASF). The frequency tuning word
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@ -584,7 +584,7 @@ class AD9910:
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pow_ += dt * ftw * self.sysclk_per_mu >> 16
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if ram_destination == -1:
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self.write64(_AD9910_REG_PROFILE0 + profile,
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(asf << 16) | (pow_ & 0xFFFF), ftw)
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(asf << 16) | (pow_ & 0xFFFF), ftw)
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else:
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if not ram_destination == RAM_DEST_FTW:
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self.set_ftw(ftw)
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@ -603,7 +603,7 @@ class AD9910:
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@kernel
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def get_mu(self, profile: TInt32 = DEFAULT_PROFILE
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) -> TTuple([TInt32, TInt32, TInt32]):
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) -> TTuple([TInt32, TInt32, TInt32]):
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"""Get the frequency tuning word, phase offset word,
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and amplitude scale factor.
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@ -625,7 +625,7 @@ class AD9910:
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def set_profile_ram(self, start: TInt32, end: TInt32, step: TInt32 = 1,
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profile: TInt32 = _DEFAULT_PROFILE_RAM,
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nodwell_high: TInt32 = 0, zero_crossing: TInt32 = 0,
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mode: TInt32 = 1):
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mode: TInt32 = 1):
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"""Set the RAM profile settings. See also AD9910 datasheet.
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:param start: Profile start address in RAM (10-bit).
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@ -645,7 +645,7 @@ class AD9910:
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"""
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hi = (step << 8) | (end >> 2)
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lo = ((end << 30) | (start << 14) | (nodwell_high << 5) |
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(zero_crossing << 3) | mode)
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(zero_crossing << 3) | mode)
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self.write64(_AD9910_REG_PROFILE0 + profile, hi, lo)
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@kernel
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@ -784,7 +784,7 @@ class AD9910:
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@portable(flags={"fast-math"})
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def turns_amplitude_to_ram(self, turns: TList(TFloat),
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amplitude: TList(TFloat), ram: TList(TInt32)):
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amplitude: TList(TFloat), ram: TList(TInt32)):
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"""Convert phase and amplitude values to RAM profile data.
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To be used with :const:`RAM_DEST_POWASF`.
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@ -796,7 +796,7 @@ class AD9910:
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"""
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for i in range(len(ram)):
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ram[i] = ((self.turns_to_pow(turns[i]) << 16) |
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self.amplitude_to_asf(amplitude[i]) << 2)
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self.amplitude_to_asf(amplitude[i]) << 2)
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@kernel
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def set_frequency(self, frequency: TFloat):
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@ -856,7 +856,7 @@ class AD9910:
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def set(self, frequency: TFloat = 0.0, phase: TFloat = 0.0,
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amplitude: TFloat = 1.0, phase_mode: TInt32 = _PHASE_MODE_DEFAULT,
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ref_time_mu: TInt64 = int64(-1), profile: TInt32 = DEFAULT_PROFILE,
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ram_destination: TInt32 = -1) -> TFloat:
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ram_destination: TInt32 = -1) -> TFloat:
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"""Set DDS data in SI units.
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See also :meth:`AD9910.set_mu`.
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@ -873,11 +873,11 @@ class AD9910:
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return self.pow_to_turns(self.set_mu(
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self.frequency_to_ftw(frequency), self.turns_to_pow(phase),
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self.amplitude_to_asf(amplitude), phase_mode, ref_time_mu,
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profile, ram_destination))
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profile, ram_destination))
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@kernel
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def get(self, profile: TInt32 = DEFAULT_PROFILE
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) -> TTuple([TFloat, TFloat, TFloat]):
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) -> TTuple([TFloat, TFloat, TFloat]):
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"""Get the frequency, phase, and amplitude.
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See also :meth:`AD9910.get_mu`.
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@ -890,7 +890,7 @@ class AD9910:
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ftw, pow_, asf = self.get_mu(profile)
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# Convert and return
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return (self.ftw_to_frequency(ftw), self.pow_to_turns(pow_),
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self.asf_to_amplitude(asf))
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self.asf_to_amplitude(asf))
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@kernel
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def set_att_mu(self, att: TInt32):
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@ -995,7 +995,7 @@ class AD9910:
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def set_sync(self,
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in_delay: TInt32,
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window: TInt32,
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en_sync_gen: TInt32 = 0):
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en_sync_gen: TInt32 = 0):
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"""Set the relevant parameters in the multi device synchronization
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register. See the AD9910 datasheet for details. The ``SYNC`` clock
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generator preset value is set to zero, and the ``SYNC_OUT`` generator is
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@ -1015,7 +1015,7 @@ class AD9910:
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(0 << 25) | # SYNC generator SYS rising edge
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(0 << 18) | # SYNC preset
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(0 << 11) | # SYNC output delay
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(in_delay << 3)) # SYNC receiver delay
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(in_delay << 3)) # SYNC receiver delay
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@kernel
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def clear_smp_err(self):
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@ -1035,7 +1035,7 @@ class AD9910:
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@kernel
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def tune_sync_delay(self,
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search_seed: TInt32 = 15) -> TTuple([TInt32, TInt32]):
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search_seed: TInt32 = 15) -> TTuple([TInt32, TInt32]):
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"""Find a stable ``SYNC_IN`` delay.
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This method first locates a valid ``SYNC_IN`` delay at zero validation
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@ -1092,7 +1092,7 @@ class AD9910:
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@kernel
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def measure_io_update_alignment(self, delay_start: TInt64,
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delay_stop: TInt64) -> TInt32:
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delay_stop: TInt64) -> TInt32:
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"""Use the digital ramp generator to locate the alignment between
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``IO_UPDATE`` and ``SYNC_CLK``.
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@ -1165,10 +1165,10 @@ class AD9910:
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t1[0] += self.measure_io_update_alignment(i, i + 1)
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t1[1] += self.measure_io_update_alignment(i + 1, i + 2)
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if ((t1[0] == 0 and t1[1] == 0) or
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(t1[0] == repeat and t1[1] == repeat)):
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(t1[0] == repeat and t1[1] == repeat)):
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# edge is not close to i + 1, can't interpret result
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raise ValueError(
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"no clear IO_UPDATE-SYNC_CLK alignment edge found")
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"no clear IO_UPDATE-SYNC_CLK alignment edge found")
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else:
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# the good delay is period//2 after the edge
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return (i + 1 + period // 2) & (period - 1)
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