mirror of https://github.com/m-labs/artiq.git
parent
12b8598b84
commit
2d14864c6d
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@ -20,9 +20,9 @@ ts = JESD204BTransportSettings(
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jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_checksum = jesd_settings.get_configuration_checksum()
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# external clk=2000MHz
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# pclock=125MHz
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# deviceclock_fpga=125MHz
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# deviceclock_dac=500MHz
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# pclock=250MHz
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# deviceclock_fpga=500MHz
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# deviceclock_dac=2000MHz
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class DACSetup(EnvExperiment):
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@ -100,7 +100,7 @@ class DACSetup(EnvExperiment):
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self.ad9154.dac_write(AD9154_SPI_PAGEINDX, 0x3) # A and B dual
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self.ad9154.dac_write(AD9154_INTERP_MODE, 1) # 2x
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self.ad9154.dac_write(AD9154_INTERP_MODE, 4) # 8x
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self.ad9154.dac_write(AD9154_MIX_MODE, 0)
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self.ad9154.dac_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)) # s16
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self.ad9154.dac_write(AD9154_DATAPATH_CTRL,
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@ -42,14 +42,10 @@ class StartupKernel(EnvExperiment):
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self.ad9154.clock_write(AD9516_OUT5, 2*AD9516_OUT5_POWER_DOWN)
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self.ad9154.clock_write(AD9516_OUT8, 1*AD9516_OUT8_POWER_DOWN)
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# DAC deviceclk, dclk/1
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self.ad9154.clock_write(AD9516_DIVIDER_0_1, AD9516_DIVIDER_0_BYPASS)
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self.ad9154.clock_write(AD9516_DIVIDER_0_2,
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0*AD9516_DIVIDER_0_DIRECT_TO_OUTPUT |
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0*AD9516_DIVIDER_0_DCCOFF)
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self.ad9154.clock_write(AD9516_OUT1,
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0*AD9516_OUT1_POWER_DOWN |
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2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
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# DAC deviceclk, clk/1
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self.ad9154.clock_write(AD9516_DIVIDER_0_2, AD9516_DIVIDER_0_DIRECT_TO_OUTPUT)
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self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
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2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
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# FPGA deviceclk, dclk/4
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self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
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