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soc/target: connect FUD to RTIO

This commit is contained in:
Sebastien Bourdeauducq 2014-09-11 23:11:22 +08:00
parent 7efc28ede1
commit 2c0b6ff4cc
1 changed files with 7 additions and 2 deletions
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9
soc/targets/artiq.py
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@ -43,12 +43,17 @@ class ARTIQMiniSoC(BaseSoC):
self.comb += platform.request("ttl_tx_en").eq(1) self.comb += platform.request("ttl_tx_en").eq(1)
rtio_pads = [platform.request("ttl", i) for i in range(4)] rtio_pads = [platform.request("ttl", i) for i in range(4)]
fud = Signal()
rtio_pads.append(fud)
self.submodules.rtiophy = rtio.phy.SimplePHY( self.submodules.rtiophy = rtio.phy.SimplePHY(
rtio_pads, rtio_pads,
{rtio_pads[1], rtio_pads[2], rtio_pads[3]}) output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3]},
mini_pads={fud})
self.submodules.rtio = rtio.RTIO(self.rtiophy) self.submodules.rtio = rtio.RTIO(self.rtiophy)
self.submodules.dds = ad9858.AD9858(platform.request("dds")) dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads)
self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus) self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
self.comb += dds_pads.fud_n.eq(~fud)
default_subtarget = ARTIQMiniSoC default_subtarget = ARTIQMiniSoC