mirror of https://github.com/m-labs/artiq.git
parent
a467b8f851
commit
2bea5e3d58
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@ -31,6 +31,7 @@ CFG_CLK_SEL1 = 21
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CFG_SYNC_SEL = 18
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CFG_RST = 19
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CFG_IO_RST = 20
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CFG_CLK_DIV = 22
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# STA status register bit offsets
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STA_RF_SW = 0
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@ -54,7 +55,7 @@ CS_DDS_CH3 = 7
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@portable
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def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
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clk_sel, sync_sel, rst, io_rst):
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clk_sel, sync_sel, rst, io_rst, clk_div):
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"""Build Urukul CPLD configuration register"""
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return ((rf_sw << CFG_RF_SW) |
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(led << CFG_LED) |
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@ -65,7 +66,8 @@ def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
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((clk_sel & 0x02) << (CFG_CLK_SEL1 - 1)) |
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(sync_sel << CFG_SYNC_SEL) |
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(rst << CFG_RST) |
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(io_rst << CFG_IO_RST))
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(io_rst << CFG_IO_RST) |
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(clk_div << CFG_CLK_DIV))
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@portable
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@ -133,6 +135,11 @@ class CPLD:
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internal MMCX. For hardware revision <= v1.2 valid options are: 0 -
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either XO or MMCX dependent on component population; 1 SMA. Unsupported
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clocking options are silently ignored.
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:param clk_div: Reference clock divider. Valid options are 0: variant
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dependent default (divide-by-4 for AD9910 and divide-by-1 for AD9912);
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1: divide-by-1; 2: divide-by-2; 3: divide-by-4.
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On Urukul boards with CPLD gateware before v1.3.1 only the default
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(0, i.e. variant dependent divider) is valid.
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:param sync_sel: SYNC (multi-chip synchronisation) signal source selection.
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0 corresponds to SYNC_IN being supplied by the FPGA via the EEM
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connector. 1 corresponds to SYNC_OUT from DDS0 being distributed to the
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@ -148,16 +155,18 @@ class CPLD:
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`sync_device` was specified).
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:param core_device: Core device name
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"""
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kernel_invariants = {"refclk", "bus", "core", "io_update"}
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kernel_invariants = {"refclk", "bus", "core", "io_update", "clk_div"}
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def __init__(self, dmgr, spi_device, io_update_device=None,
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dds_reset_device=None, sync_device=None,
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sync_sel=0, clk_sel=0, rf_sw=0,
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sync_sel=0, clk_sel=0, clk_div=0, rf_sw=0,
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refclk=125e6, att=0x00000000, sync_div=None,
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core_device="core"):
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self.core = dmgr.get(core_device)
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self.refclk = refclk
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assert 0 <= clk_div <= 3
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self.clk_div = clk_div
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self.bus = dmgr.get(spi_device)
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if io_update_device is not None:
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@ -177,7 +186,8 @@ class CPLD:
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self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0,
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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sync_sel=sync_sel, rst=0, io_rst=0)
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sync_sel=sync_sel,
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rst=0, io_rst=0, clk_div=clk_div)
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self.att_reg = int32(int64(att))
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self.sync_div = sync_div
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