From 2bb90a4449f03458ec747d023ed41c049ab4e49c Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 21 Sep 2016 02:29:05 +0200 Subject: [PATCH] pipistrello: shrink a few more fifos --- artiq/gateware/targets/pipistrello.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 1ef83bd46..98e6555bb 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -176,7 +176,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i), self.rtio_crg.rtiox4_stb) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256, + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128, ofifo_depth=4)) # the last TTL is used for ClockGen @@ -223,7 +223,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = dds.AD9858(dds_pins, 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, - ofifo_depth=256, + ofifo_depth=128, ififo_depth=4)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)